IP Library Granted Patent US 9,325,312
Granted Patent B1
US 9,325,312 · App. 14/568,093 · Granted Apr 26, 2016

Input control circuit for analog device

Inventors: Mayank Jain (Ambala Cantt, IN); Sanjoy K. Dey (Noida, IN)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H03K17/687
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Quick Facts
Patent No.
US 9,325,312
App. No.
14/568,093
Granted
Apr 26, 2016
Kind
B1
Abstract

An input control circuit that can be used to drive analog switches of analog modules such as an analog-to-digital converter (ADC) enables a sampling switch to receive a higher input voltage than the voltage rating of the devices comprising the sampling switch without risk of damage and without the need for a resistor divider network. The input control circuit and switch both receive an input voltage to be processed and the input control circuit generates a control signal for the switch that is derived from a pre-charged capacitor. The control circuit permits the design and manufacture of high voltage analog modules using low voltage devices, which can save on mask costs without any performance trade-offs.

Claims (22)

1. A control circuit for an analog device that includes a sampling switch arrangement that receives an analog voltage to be sampled and has a control input, the control circuit comprising:

an input terminal for receiving the analog voltage to be sampled;

an output terminal for connection to the control input of the sampling switch arrangement;

a first switch arrangement;

a charging capacitor operably coupled between the input terminal and the first switch arrangement; and

a charging circuit operably coupled to the charging capacitor for charging the charging capacitor to a preset voltage,

wherein the first switch arrangement connects the output terminal to ground in an ‘off’ mode of operation and transfers a voltage from a terminal of the charging capacitor to the output terminal in an ‘on’ mode of operation.

2. The control circuit of claim 1 wherein the first switch arrangement comprises:

a P MOSFET (P channel metal oxide semiconductor field effect transistor) connected in series with an N MOSFET (N channel MOSFET), for connecting the output terminal to ground by way of the N MOSFET in the ‘off’ mode and transferring a voltage from a terminal of the charging capacitor to the output terminal by way of the P MOSFET in the ‘on’ mode.

3. The control circuit of claim 2 , wherein the charging circuit sets a first terminal of the charging capacitor to a voltage equal to the received analog voltage plus a charging voltage, and sets a second terminal of the charging capacitor to the received analog voltage, and

wherein a source terminal of the P MOSFET is connected to the first terminal of the charging capacitor, and

wherein the control circuit includes a second switch arrangement that connects a gate terminal of the P MOSFET to a supply voltage in the ‘off’ mode and to the second terminal of the charging capacitor in the ‘on’ mode.

4. An analog device comprising a control circuit and a sampling switch, the control circuit comprising:

an input terminal for receiving an analog voltage to be sampled;

an output terminal;

a first switch;

a charging capacitor operably coupled between the input terminal and the first switch; and

a charging circuit operably coupled to the charging capacitor for charging the charging capacitor to a preset voltage,

wherein the first switch connects the output terminal to ground in an ‘off’ mode of operation and transfers a voltage from a terminal of the charging capacitor to the output terminal in an ‘on’ mode of operation, and

wherein the sampling switch comprises:

a first N MOSFET (metal oxide semiconductor field effect transistor) connected in series between second and third N MOSFETs,

wherein a drain terminal of the second N MOSFET receives the analog voltage to be sampled, a drain terminal of the third N MOSFET comprises an output of the sampling switch, gate terminals of the second and third N MOSFETs are connected to the charging capacitor, and a gate terminal of the first N MOSFET is connected to the output terminal of the control circuit.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2014
From: JAIN, MAYANK; DEY, SANJOY K.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034484/0238 →