Low power digital self-gated binary counter
View Patent ↗An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
1. An n-bit counter circuit, comprising:
a plurality of cascaded counter sub-modules including at least first and second cascaded counter sub-modules, the first counter sub-module being at least a lower-order counter sub-module relative to the second counter sub-module, the second counter sub-module being a higher-order counter sub-module relative to the first counter sub-module, as well as being a lower-order counter sub-module relative to subsequent cascaded counter sub-modules; and
control logic coupled to the first counter sub-module, wherein:
the control logic includes a clock-gating integrated cell (CGIC) that clocks at least the second counter sub-module dependent on a logical combination of outputs of at least the first counter sub-module, and provides a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules dependent on a logical combination of the outputs of at least the second counter sub-module; and
the control logic does not include any intervening memory device between the first counter sub-module and the CGIC for use in resolution of a logical combination of outputs,
wherein:
the CGIC is coupled between the first counter sub-module and the second counter sub-module and controls a clock input of the second counter sub-module;
the CGIC comprises a latch having an output operatively coupled to a first input of a two-input AND gate, wherein:
the latch is operated by a changing level of a clock signal;
the clock signal is operatively coupled to a second input of the two-input AND gate; and
an input to the latch is a logically ANDed output of the first counter sub-module.
2. The n-bit counter circuit of claim 1 , wherein at least the n-bit counter circuit is fabricated as part of an integrated circuit.
3. The n-bit counter circuit of claim 1 , wherein a fan-in of a first tier of control logic gates is equal to a bit depth of at least one of the plurality of cascaded counter sub-modules.
4. The n-bit counter circuit of claim 1 , wherein:
the first counter sub-module is operable to count two least-significant bits of the counter circuit;
the second counter sub-module is operable to count a next two more-significant bits of the counter circuit;
the input to the latch is the logically ANDed output of the first counter sub-module; and
a least-significant bit input to an AND gate operably coupled to the output of the first counter sub-module is not an inverted input.
5. The n-bit counter circuit of claim 1 , further comprising respective second CGICs between each consecutive pair of the plurality of counter sub-modules.
6. The n-bit counter circuit of claim 1 , wherein:
the first counter sub-module is operable to count two least-significant bits of the counter circuit; and
the second counter sub-module is operable to count a next two more-significant bits of the counter circuit.
7. The n-bit counter circuit of claim 1 , wherein the n-bit counter is a higher-than-4-bit counter.
8. The n-bit counter circuit of claim 1 , comprising a control logic instance per instance of a higher-order counter sub-module of the counter circuit.
9. The n-bit counter circuit of claim 1 , wherein the second counter sub-module of the counter circuit is the next higher-order counter sub-module after the first counter sub-module.
10. The n-bit counter circuit of claim 1 , wherein:
the plurality of cascaded counter sub-modules comprises a first lowest-order counter sub-module followed by a second higher-order counter sub-module cascaded off the first lowest-order counter sub-module; and
each subsequent counter sub-module cascades off a previous counter sub-module and is a yet-higher-order counter sub-module.
11. The n-bit counter circuit of claim 1 , wherein the first counter sub-module and the second counter sub-module form an initial 4-bit counter sub-portion, wherein:
the first counter sub-module is a first 2-bit counter sub-module of the initial 4-bit counter sub-portion, arranged to count two least-significant output bits Q 0 and Q 1 of the n-bit counter circuit;
the second counter sub-module is a second 2-bit counter sub-module of the initial 4-bt counter sub-portion, arranged to count a next two more-significant output bits Q 2 and Q 3 of the n-bit counter circuit;
the control logic is arranged to control a clock of the second 2-bit counter sub-module dependent on the outputs of the first 2-bit counter sub-module; and
the control logic comprises:
the CGIC operable to clock gate the second 2-bit counter sub-module, the CGIC operable to receive the logical AND combination of Q 1 and Q 0 without the logical combination passing through any intervening memory device.
12. The n-bit counter circuit of claim 11 , wherein neither Q 1 nor Q 2 are inverted in the logical combination of Q 1 and Q 0 .
13. The n-bit counter circuit of claim 12 , wherein the logical combination of Q 1 and Q 0 is directly connected as an input to the CGIC.