Granted Patent B2

US 9,716,505 · App. 14/570,946 · Granted Jul 25, 2017

Abstract

Claims (42)

1. A circuit comprising:

a multiplier circuit portion;

a first duty cycle correction (DCC) circuit portion; and

a clock gating circuit portion,

wherein the multiplier circuit portion, the first DCC circuit portion, and the clock gating circuit portion are all coupled in series with one another between an input port and an output port of the circuit,

wherein the circuit is capable of receiving at the input port a first clock signal having a first frequency and, based at least indirectly upon the first clock signal, outputting a second clock signal having a second frequency that is related by a factor to the first frequency,

wherein the first DCC circuit portion includes a plurality of buffers coupled in series between a DCC circuit portion input terminal and a DCC circuit portion output terminal, further includes an operational amplifier having an inverting terminal and a non-inverting terminal, the non-inverting terminal being coupled to the DCC circuit portion output terminal by way of a resistor and coupled to ground by way of a capacitor, and additionally includes a P/N adjust circuit portion that is configured to receive an output signal from the operational amplifier and provide at least one further signal based at least indirectly upon the output signal to adjust at least one parameter of one or more of the buffers of the plurality of buffers, and

wherein the clock gating circuit portion includes at least one logic gate coupled between a clock gating circuit portion input terminal and a clock gating circuit portion output terminal.

2. The circuit of claim 1 , wherein the clock gating circuit portion input terminal is the input port, and wherein the clock gating circuit portion output terminal is directly coupled to either the first DCC circuit portion or the multiplier circuit portion.

3. The circuit of claim 2 , wherein if the clock gating circuit portion output terminal is coupled to the first DCC circuit portion, then the first DCC circuit portion is coupled in series between the clock gating circuit portion and the multiplier circuit portion and an additional DCC circuit output terminal of an additional DCC circuit portion coupled to the multiplier circuit is the output port of the circuit.

4. The circuit of claim 2 , wherein if the clock gating circuit portion output terminal is coupled to the multiplier circuit portion, then the multiplier circuit portion is coupled in series between the clock gating circuit portion and the first DCC circuit portion and a DCC circuit portion output terminal of the first DCC circuit portion is the output port of the circuit.

5. The circuit of claim 1 , further comprising an additional DCC circuit portion, wherein the clock gating circuit portion is coupled in series between the additional DCC circuit portion and the multiplier circuit portion, and wherein the multiplier circuit portion is coupled in series between the clock gating circuit portion and the first DCC circuit portion.

6. The circuit of claim 1 , wherein the multiplier circuit portion is a multiply-by-two circuit portion that is configured to receive either the first clock signal having the first frequency or a first additional clock signal that also has the first frequency and that is at least indirectly related to the first clock signal, and to output either the second clock signal having the second frequency or a second additional clock signal based at least indirectly the second clock signal, and wherein the factor by which the first and second frequencies are related is two, such that the second frequency is two times the first frequency.

7. The circuit of claim 1 , wherein the multiplier circuit portion includes a multiplier circuit input terminal, a multiplier circuit output terminal, and an EX-OR gate, wherein the multiplier circuit input terminal is directly coupled to a first EX-OR gate input terminal of the EX-OR gate and is indirectly coupled to a second EX-OR gate input terminal of the EX-OR gate by way of a time delay circuit portion, and wherein an EX-OR gate output terminal of the EX-OR gate is, or is coupled directly to, the multiplier circuit output terminal.

8. The circuit of claim 1 wherein, due to an operation of the first DCC circuit

portion, the second clock signal satisfies a first duty cycle criterion, and wherein the first duty cycle criterion is that a duty cycle of the second clock signal either equals or substantially equals 50%.

9. A system for implementation in an integrated circuit, the system comprising:

a phase-locked loop (PLL) circuit portion that receives a first clock signal;

at least one circuit portion that is configured to receive a second clock signal; aid

at least one intermediate circuit portion that is configured to receive at an input port the first clock signal or a first intermediate signal based at least indirectly upon the first clock signal, the first clock signal or first intermediate signal having a first frequency, and to provide at an output port the second clock signal or a second intermediate signal upon which the second clock signal is based at least indirectly, the second clock signal or second intermediate signal having a second frequency related to the first frequency by a factor,

wherein the at least one intermediate circuit portion includes at least a first intermediate circuit portion and a second intermediate circuit portion that are respectively coupled in series with one another between the input and output ports, wherein the first intermediate circuit portion is a first multiplication circuit portion and the second intermediate circuit portion is a first duty cycle correction (DCC) circuit portion;

an additional intermediate circuit portion including an additional DCC circuit portion and an additional multiplication circuit portion, wherein the additional intermediate circuit portion is coupled to a PLL input port of the PLL circuit portion; and

a further intermediate circuit portion that is configured to receive at a further input port the first clock signal to provide at a further output port a further clock signal, the further clock signal having the second frequency, wherein the further intermediate circuit portion includes a further multiplication circuit portion and a further DCC circuit portion.

10. The system of claim 9 , wherein the first multiplication circuit portion includes a first input terminal and a first output terminal, wherein the first DCC circuit portion includes a second input terminal and a second output terminal, wherein the first output terminal is coupled directly to the second input terminal, and wherein the second output terminal constitutes the output port of the at least one intermediate circuit portion.

11. The system of claim 10 , wherein the first input terminal constitutes the input port of the at least one intermediate circuit portion.

12. The system of claim 10 , wherein the at least one intermediate circuit portion additionally includes a clock gating circuit portion that includes a third input terminal and a third output terminal, wherein the third output terminal is coupled directly to the first input terminal.

13. The system of claim 12 , wherein the third input terminal constitutes the input port of the at least one intermediate circuit portion.

14. The system of claim 12 , wherein the at least one intermediate circuit portion additionally includes a fourth DCC circuit portion that includes a fourth input terminal and a fourth output terminal, wherein the fourth output terminal is coupled directly to the third input terminal, and wherein the fourth input terminal constitutes the input port of the at least one intermediate circuit portion.

15. The system of claim 10 , wherein the at least one intermediate circuit portion additionally includes a fourth DCC circuit portion that includes a third input terminal and a third output terminal, wherein the third output terminal is coupled directly to the first input terminal, and wherein the third input terminal constitutes the input port of the at least one intermediate circuit portion.

16. The system of claim 9 , further comprising a clock gating circuit portion and a fourth DCC circuit portion, wherein the clock gating circuit portion includes a first input terminal and a first output terminal, wherein the fourth DCC circuit portion includes a second input terminal and a second output terminal, wherein the first multiplication circuit portion includes a third input terminal and a third output terminal, wherein the first DCC circuit portion includes a fourth input terminal and a fourth output terminal, wherein the first output terminal is coupled directly to the second input terminal, wherein the second output terminal is coupled directly to the third input terminal, wherein the third output terminal is coupled directly to the fourth input terminal, and wherein the first input terminal constitutes the input port of the at least one intermediate circuit portion and the fourth output terminal constitutes the output port of the at least one intermediate circuit portion.

17. A system for implementation in an integrated circuit, the system comprising:

a phase-locked loop (PLL) circuit portion that receives a first clock signal;

at least one circuit portion that is configured to receive a second clock signal;

at least one intermediate circuit portion that is configured to receive at an input port the first clock signal or a first intermediate signal based at least indirectly upon the first clock signal, the first clock signal or first intermediate signal having a first frequency, and to provide at an output port the second clock signal or a second intermediate signal upon which the second clock signal is based at least indirectly, the second clock signal or second intermediate signal having a second frequency related to the first frequency by a factor,

wherein the at least one intermediate circuit portion includes at least a first intermediate circuit portion and a second intermediate circuit portion that are respectively coupled in series with one another between the input and output ports, wherein the first intermediate circuit portion is a multiplication circuit portion and the second intermediate circuit portion is a first duty cycle correction (DCC) circuit portion;

a clock gating circuit portion; and

an additional DCC circuit portion, wherein the clock gating circuit portion includes a first input terminal and a first output terminal, wherein the additional DCC circuit portion includes a second input terminal and a second output terminal, wherein the multiplication circuit portion includes a third input terminal and a third output terminal, wherein the first DCC circuit portion includes a fourth input terminal and a fourth output terminal, and

wherein the first output terminal is coupled directly to the second input terminal, wherein the second output terminal is coupled directly to the third input terminal, wherein the third output terminal is coupled directly to the fourth input terminal, and wherein the first input terminal constitutes the input port of the at least one intermediate circuit portion and the fourth output terminal constitutes the output port of the at least one intermediate circuit portion.

18. The system of claim 17 , further comprising:

a further intermediate circuit portion including a further DCC circuit portion and a further multiplication circuit portion, wherein the further intermediate circuit portion is coupled to a PLL input port of the PLL circuit portion.

19. The system of claim 17 , further comprising:

a further intermediate circuit portion that is configured to receive at a further input port the first clock signal to provide at a further output port a further clock signal, the further clock signal having the second frequency, wherein the further intermediate circuit portion includes a further multiplication circuit portion and a further DCC circuit portion.

Assignments (11)