Low power configuration for USB (Universal Serial Bus) devices
The present disclosure provides for a method and semiconductor device for low power configuration. In one embodiment, a method includes receiving a packet from a host device, where the packet is received at a USB (Universal Serial Bus) device. The method also includes detecting, by the USB device, that the packet includes an endpoint address of a low power endpoint. The method also includes entering a low power mode state, in response to the detecting, where the USB device includes a USB clock domain that includes an internal reference clock (IRC) and clock recovery logic, and a clock tree block located outside of the USB clock domain. The entering the low power mode state includes disabling the clock tree block, and clocking the USB clock domain using the IRC and clock recovery logic.
1. A method comprising:
receiving a packet from a host device, wherein
the packet is received at a USB (Universal Serial Bus) device;
detecting, by the USB device, that the packet includes an endpoint address of a low power endpoint; and
entering a low power mode state, in response to the detecting, wherein
the USB device comprises
a USB clock domain that includes an internal reference clock (IRC) and clock recovery logic, and
a clock tree block located outside of the USB clock domain, and
the entering the low power mode state comprises
disabling the clock tree block, and
clocking the USB clock domain using the IRC and clock recovery logic.
2. The method of claim 1 , wherein the entering the low power mode state further comprises:
powering down peripheral hardware on the USB device located outside of the USB clock domain.
3. The method of claim 1 , further comprising:
during the low power mode state, receiving a subsequent packet from the host device; and
detecting whether the subsequent packet includes a packet identifier (PID) that matches a wakeup PID.
4. The method of claim 3 , further comprising:
in response to detection that the PID matches the wakeup PID, enabling the clock tree block and clocking the USB clock domain using the clock tree block.
5. The method of claim 3 , further comprising:
in response to detection that the PID matches the wakeup PID, powering up peripheral hardware on the USB device located outside of the USB clock domain.
6. The method of claim 3 , further comprising:
in response to detection that the PID does not match the wakeup PID, responding to the host device with a negative acknowledgement (NAK) packet.
7. The method of claim 3 , wherein
the wakeup PID is one of a plurality of wakeup PIDs configured as wakeup sources for the USB device.
8. The method of claim 1 , further comprising:
during the low power mode state, maintaining the low power endpoint.
9. The method of claim 1 , wherein
the low power endpoint reserves zero bandwidth for data transfer on a USB interconnect between the USB device and the USB host.
10. The method of claim 1 , wherein
the low power endpoint is one of a plurality of low power endpoints configured on the USB device.
11. The method of claim 1 , wherein
the USB device enters the low power mode state further in response to criteria being met, and
the criteria indicates that the USB device should enter low power mode state in response to receipt of the endpoint address of the low power endpoint.
12. The method of claim 11 , wherein
the criteria further indicates that the USB device should enter low power mode state after a period of idle time.
13. A semiconductor device comprising:
a clock tree block;
peripheral hardware; and
a USB (Universal Serial Bus) clock domain partitioned from the clock tree block and the peripheral hardware, the USB clock domain comprising:
an internal reference clock (IRC) configured to output a clock signal,
clock recovery logic configured to maintain accuracy of the clock signal, and packet processing logic configured to
receive a packet from a host device;
enter a low power mode state, in response to detection that the packet includes an endpoint address of a low power endpoint,
disable the clock tree block, and
enable the IRC and clock recovery logic to clock the USB clock domain during the low power mode state.
14. The semiconductor device of claim 13 , wherein the packet processing logic is further configured to
power down the peripheral hardware on entry to the low power mode state.
15. The semiconductor device of claim 13 , wherein
the packet processing logic is further configured to
receive a subsequent packet from the host device during the low power mode state, and
the packet processing logic comprises a wakeup decoder configured to detect whether the subsequent packet includes a packet identifier (PID) that matches a wakeup PID.
16. The semiconductor device of claim 15 , wherein
the wakeup decoder is configured to output a wakeup interrupt signal in response to a detection that the PID matches the wakeup PID, and
the wakeup interrupt signal is configured to trigger a wakeup interrupt routine that enables the clock tree block.
17. The semiconductor device of claim 16 , wherein
the wakeup interrupt routine further powers up the peripheral hardware.
18. The semiconductor device of claim 15 , wherein
the packet processing logic is configured to respond to the host device with a negative acknowledgement (NAK) packet in response to detection that the PID does not match the wakeup PID.
19. A semiconductor device comprising:
a USB (Universal Serial Bus) clock domain comprising:
an internal reference clock (IRC) configured to output a clock signal,
clock recovery logic configured to maintain accuracy of the clock signal, and
packet processing logic configured to
receive a packet from a host device;
enter a low power mode state, in response to detection that the packet includes an endpoint address of a low power endpoint, and
enable the IRC and clock recovery logic to clock the USB clock domain during the low power mode state.
20. The semiconductor device of claim 19 , wherein
the packet processing logic is further configured to
receive a subsequent packet from the host device during the low power mode state, and
the packet processing logic comprises a wakeup decoder configured to output a wakeup interrupt signal in response to a detection that a packet identifier (PID) matches a wakeup PID.