FRACTIONAL AND INTEGER RATIO POLYPHASE INTERPOLATION FILTER
A fractional and integer ratio polyphase interpolation filter changes the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N. The clock rate required to evaluate the output signal is M/N.
1 . A method of changing the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N, comprising:
storing, at plural taps of a digital delay line a delayed sequence of samples of the input signal;
maintaining an accumulated sample index S; and
calculating samples of an output digital signal by:
multiplying the sample of the input signal stored at each tap T by filter coefficients provided by a filter coefficient calculator based in part on S;
summing the multiplied tap values to provide the filtered output signal sample;
incrementing S by N and if the result is greater than the next integer multiple of M greater than S, then the digital delay line is clocked to move the samples of the input signal along the taps and introduce the next sample of the input signal; and
returning to the multiplying step.
2 . The method of claim 1 , wherein M is greater than N.
3 . The method of claim 1 , wherein the values on M and N are programmable.
4 . The method of claim 1 , wherein the starting value of S is zero.
5 . The method of claim 1 , wherein the clock rate required to produce the output signal is M/N times the input.
6 . The method of claim 1 , wherein the incrementing of S by N is calculated modulo M.
7 . The method of claim 1 , wherein the multiplication coefficient component h for each tap in the delay line is h [S] for the first tap, h [S+M] for the next tap, h [S+2M] for the next tap and so on in sequence.
8 . The method of claim 7 , wherein the sequence for the multiplication coefficient component h continues until the tap for which h [S+(L−1)*M] wherein L is evaluated by ceil(T/(K−1)), wherein T is the number of taps in the delay line and K is the minimum interpolation rate supported in the filter design.
9 . The method of claim 8 , wherein the value of a given multiplication coefficient component h is zero if the coefficient index is greater than (T−1).
10 . A filter configured to change the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N, comprising:
a digital delay line having plural taps that store a delayed sequence of samples of the input signal;
a multiplier for each tap;
an adder coupled to the multipliers;
a filter coefficient calculator for providing filter coefficients; and
control logic that maintains an accumulated sample index S and causes the filter to calculate samples of an output digital signal by:
the multipliers multiplying the sample of the input signal stored at each tap T by filter coefficients provided the filter coefficient calculator based in part on S;
the adder summing the multiplied tap values to provide the filtered output signal sample;
the control logic incrementing S by N and if the result is greater than the next integer multiple of M greater than S, then the digital delay line is clocked to move the samples of the input signal along the taps and introduce the next sample of the input signal; and
returning to the multiplying step.
11 . The filter of claim 10 , wherein M is greater than n.
12 . The filter of claim 10 , wherein filter is configured such that the values on M and N are programmable.
13 . The filter of claim 10 , wherein the starting value of S is zero.
14 . The filter of claim 10 , wherein the clock rate required to produce the output signal is M/N times the input.
15 . The filter of claim 10 , wherein the control logic is configured such that the incrementation of S by N is calculated modulo m.
16 . The filter of claim 10 , further comprising a filter coefficient calculator that calculates the multiplication coefficient component h for each tap in the delay line as h [S] for the first tap, h [S+M] for the next tap, h [S+2M] for the next tap, and so on in sequence.
17 . The filter of claim 16 , wherein the sequence for the multiplication coefficient component h continues until the tap for which h [S+(L−1)*M] wherein L is evaluated by ceil (T/(K−1)) and wherein T is the number of taps in the delay line and K is the minimum interpolation rate supported in the filter design.
18 . The filter of claim 17 , wherein the value of a given multiplication coefficient component h is zero if the coefficient index is greater than (T−1).
19 . A method of changing the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N, comprising:
storing, at plural taps of a digital delay line, a delayed sequence of samples of the input signal;
calculating samples of an output digital signal using a polyphase filter;
maintaining a signal index S incremented by N each calculation; and
clocking the digital delay line to introduce the next input sample each time S is incremented beyond a multiple of M.
20 . The method of claim 19 , wherein filter coefficients applied by the polyphase filter to multiply the input signal sample values at each tap are determined in part based on S.