Granted Patent B1

US 9,209,790 · App. 14/576,201 · Granted Dec 8, 2015

Abstract

Claims (40)

1. A comparator, comprising:

a voltage divider that develops a midpoint voltage between a voltage on a power rail and a voltage on a low-voltage rail;

a current mirror comprising a first transistor stack connected to a second transistor stack, wherein:

the current mirror establishes a first current in the first transistor stack, the first current determined by the midpoint voltage, the first current developing a first bias signal at a first bias node; and

the current mirror establishes in the second transistor stack a second current proportional to the first current, wherein the second current develops a second bias signal at a second bias node;

a compensation circuit coupled between the first and second bias nodes that prevents oscillations in the comparator;

a first inverter comprising a third transistor stack, wherein the first inverter receives a reference signal and establishes a third current through the third transistor stack, the third current being determined partially by the reference signal and partially by the first and second bias signals; and

a second inverter comprising a fourth transistor stack, wherein the second inverter receives an input signal for comparison to the reference signal and establishes a fourth current through the fourth transistor stack, the fourth current being determined partially by the input signal and partially by the first and second bias signals, the fourth transistor stack generates an output signal the magnitude of which is an indication whether the input signal is greater than or less than the reference signal.

2. The comparator of claim 1 , wherein the fourth transistor stack is no more than two transistors in height between the power rail and the low-voltage rail.

3. The comparator of claim 2 , wherein each of the first, second, and third transistor stacks is no more than two transistors in height between the power rail and the low-voltage rail.

4. The comparator of claim 1 , further comprising:

N additional inverter stages, where N is an integer greater than or equal to one, the first one of the N additional inverter stages receiving the output of the fourth transistor stack as an input and providing an output that is a binary-valued inverse of the input; and

each subsequent one of the N−1 additional inverter stages receiving the output from a preceding inverter stage as an input and providing an output that is a binary-valued inverse of the input.

5. The comparator of claim 1 , wherein transistors in the fourth transistor stack are sized larger than corresponding transistors in the third transistor stack.

6. The comparator of claim 1 , wherein the comparator is fabricated as part of an integrated circuit.

7. The comparator of claim 1 , further comprising a switch (MP 10 ) connected in series with the voltage divider between the power rail and the low-voltage rail to power down the voltage divider when the comparator is turned off.

8. The comparator of claim 1 , wherein the compensation circuit comprises a resistor and a capacitor connected in series.

9. The comparator of claim 1 , further comprising:

a first switch coupled between the first bias node and the power rail;

a second switch coupled between the gates of the first and third transistors and the power rail;

a third switch coupled between the output of the fourth transistor stack and the power rail;

a fourth switch coupled between the second bias node and the low-voltage rail; and

a fifth switch coupled between the input signal and the low-voltage rail, wherein the first, second, third, and fourth switches are controlled to control whether the comparator is turned on or off.

10. The comparator of claim 1 , wherein the third transistor stack comprises a transistor configured to receive the predetermined reference signal on a gate terminal, the transistor having a channel width-to-length ratio, the third current also partially determined by the width-to-length ratio of the transistor.

11. The comparator of claim 1 , wherein the fourth transistor stack comprises a transistor configured to receive the input signal on a gate terminal, the transistor having a channel width-to-length ratio, the fourth current also partially determined by the width-to-length ratio of the transistor.

12. The comparator of claim 1 , wherein:

sizes of transistors in the first transistor stack are equivalent to sizes of corresponding transistors in the second transistor stack; and

sizes of transistors in the third transistor stack are equivalent to sizes of corresponding transistors in the fourth transistor stack.

13. A low voltage headroom comparator, comprising:

first and second transistors having conduction paths in series between a power supply rail and a low voltage rail, a bias node formed at a connection of drains of the first and second transistors, a gate of the second transistor coupled to a voltage reference midpoint between the power supply rail and the low voltage rail;

third and fourth transistors having conduction paths in series between the power supply rail and the low voltage rail, the first and third transistors being configured as a current mirror;

fifth and sixth transistors having conduction paths in series between the power supply rail and the low voltage rail, a gate of the sixth transistor configured to receive a predetermined reference signal, a gate of the fourth transistor coupled to a drain of the sixth transistor;

seventh and eight transistors having conduction paths in series between the power supply rail and the low voltage rail, the comparator providing an output at a connection of drains of the seventh and eighth transistors, a gate of the eighth transistor configured to receive a magnitude varying input signal, a gate of the fifth and seventh transistors coupled to the bias node; and

a compensation circuit coupled between the gate of the fourth transistor and the bias node.

14. A low voltage, self-biased, high speed comparator, comprising:

a first transistor stack including first and second transistors having conduction paths in series between a power supply rail and a low voltage rail, a bias node formed at a connection of drains of the first and second transistors, a gate of the second transistor coupled to a voltage reference midpoint between the power supply rail and the low voltage rail, the first transistor stack having no more than two transistor conduction paths between the power rail and the low voltage rail;

a second transistor stack including third and fourth transistors having conduction paths in series between the power supply rail and the low voltage rail, the first and third transistors being configured as a current mirror, the second transistor stack having no more than two transistor conduction paths between the power rail and the low voltage rail;

a compensation circuit coupled between a gate of the fourth transistor and the bias node;

a third transistor stack including fifth and sixth transistors having conduction paths in series between the power supply rail and the low voltage rail, a gate of the sixth transistor configured to receive a predetermined reference signal, a gate of the fourth transistor coupled to a drain of the sixth transistor, the third transistor stack having no more than two transistor conduction paths between the power rail and the low voltage rail; and

a fourth transistor stack including seventh and eight transistors having conduction paths in series between the power supply rail and the low voltage rail, the comparator providing an output at a connection of drains of the seventh and eighth transistors, a gate of the eighth transistor configured to receive a magnitude varying input signal, a gate of the fifth and seventh transistors coupled to the bias node, the fourth transistor stack having no more than two series coupled conduction paths between the power rail and the low voltage rail.

Assignments (14)