Substrate core via structure
By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.
1. A method of making a packaged semiconductor structure, the method comprising:
forming a plurality of electrically conductive lines over an electrically non-conductive base layer;
shaping the plurality of electrically conductive lines through a plurality of rollers along a dimension substantially parallel to at least one of the plurality of electrically conductive lines to form a plurality of fillable structures;
filling the plurality of fillable structures with an electrically nonconductive material; and
grinding the electrically nonconductive material and at least one of the plurality of fillable structures to a top surface and a bottom surface to form a plurality of vias, wherein at least one of the plurality of vias extends from the top surface to the bottom surface.
2. The method of claim 1 , further comprising:
laminating a portion of the plurality of electrically conductive lines before shaping the plurality of electrically conductive lines.
3. The method of claim 2 , wherein
laminating the portion of the plurality of electrically conductive lines is done with one of a group consisting of: epoxy, resin, synthetic epoxy-resin, glass fiber substrate, or paper fiber material.
4. The method of claim 1 , wherein
at least one of the plurality of electrically conductive lines has a cross-section of one of a group consisting of: circular, square, triangular, quadrilateral, hexagonal, or rectangular cross-section.
5. The method of claim 1 , wherein
grinding the electrically nonconductive material is done through one of a group consisting of: chemical, physical, mechanical, or chemical-mechanical polishing processes.
6. The method of claim 1 , wherein shaping the plurality of conductive lines comprises shaping a first conductive line through a plurality of rollers of a first shape and shaping a second conductive line through a plurality of rollers of a second shape.
7. The method of claim 1 , wherein the plurality of vias comprises a first via extending from the top surface to the bottom surface at a first angle and a second via extending from the top surface to the bottom surface at a second angle.
8. A method of making a packaged semiconductor structure, the method comprising:
forming a plurality of electrically conductive lines over an electrically non-conductive base layer;
shaping the plurality of electrically conductive lines through a plurality of rollers along a dimension substantially perpendicular to at least one of the plurality of electrically conductive lines to form a plurality of fillable structures;
filling the plurality of fillable structures with a nonconductive material; and
grinding the nonconductive material and at least one of the plurality of fillable structures to a top surface and a bottom surface to form a plurality of vias, wherein at least one of the plurality of vias extends from the top surface to the bottom surface.
9. The method of claim 8 , further comprising:
laminating a portion of the plurality of electrically conductive lines before shaping the plurality of electrically conductive lines.
10. The method of claim 8 , wherein
laminating the plurality of electrically conductive lines is done with one of a group consisting of: epoxy, resin, cured epoxy-resin synthetic, glass fiber substrate, or paper fiber material.
11. The method of claim 8 , wherein
at least one of the plurality of electrically conductive lines has a cross-section of one of a group consisting of: circular, square, triangular, quadrilateral, hexagonal, or rectangular cross-section.
12. The method of claim 8 , wherein
grinding the nonconductive material is done through one of a group consisting of: chemical, physical, mechanical, or chemical-mechanical polishing processes.
13. The method of claim 8 , wherein shaping the plurality of conductive lines comprises shaping a first conductive line through a plurality of rollers of a first shape and shaping a second conductive line through a plurality of rollers of a second shape.
14. The method of claim 9 , wherein the plurality of vias comprises a first via extending from the top surface to the bottom surface at a first angle and a second via extending from the top surface to the bottom surface at a second angle.
15. A packaged semiconductor structure, the structure comprising:
a via layer comprising a top surface and a bottom surface;
a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface;
a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and
a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle;
wherein the first angle is associated with a structure of a first corrugating element and the second angle is associated with a structure of a second corrugating element.
16. The packaged semiconductor structure of claim 15 , wherein
a portion of the plurality of vias has a cross-section of one of a group consisting of:
circular, square, triangular, quadrilateral, hexagonal, or rectangular cross-section.
17. The packaged semiconductor structure of claim 15 , wherein the first angle is equal to the second angle.
18. The packaged semiconductor structure of claim 15 , wherein the first angle is different from the second angle.
19. The packaged semiconductor structure of claim 15 , wherein the first via has a cross-section of a first shape and the second via has a cross-section of a second shape.