Driver circuit receiving a regulated pre-driver supply voltage
A driver circuit includes first and second pluralities of series-connected inverters for pre-driving an input signal to first and second drive transistors, and a plurality of capacitors. The first and second drive transistors coupled to the last inverter of the first and second pluralities of series-connected inverters. Each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters. In another embodiment, a plurality of discharge circuits is coupled to the first plurality of series-connected inverters. Another embodiment includes a combination of capacitors and discharge circuits coupled to the first plurality of series-connected inverters. The embodiments provide a driver circuit with high frequency voltage regulation.
1. A driver circuit comprising:
a first plurality of series-connected inverters, each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter;
a second plurality of series-connected inverters, each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input of a subsequent inverter, the second plurality of series-connected inverters having a same number of inverters as the first plurality of series-connected inverters;
a first transistor having a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output terminal of a last inverter in the first plurality of series-connected inverters, and a second current electrode coupled to an output terminal;
a second transistor having a first current electrode coupled to the output terminal, a control electrode coupled to the output terminal of a last inverter in the second plurality of series-connected inverters, and a second current electrode coupled to a second power supply terminal; and
a plurality of capacitors, each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters.
2. The driver circuit of claim 1 , wherein the first plurality of series-connected inverters receive a first power supply voltage and the second plurality of series-connected inverters receive a second power supply voltage different from the first power supply voltage.
3. The driver circuit of claim 1 , wherein each inverter of the first plurality of series-connected inverters has a first power supply terminal coupled to receive the first power supply voltage, and a second power supply terminal coupled to receive a second power supply voltage regulated to a predetermined voltage level above ground.
4. The driver circuit of claim 3 , wherein each inverter of the second plurality of series-connected inverters has a first power supply terminal coupled to receive a third power supply voltage, and a second power supply voltage terminal coupled to ground, wherein the third power supply voltage is less than the first power supply voltage.
5. The driver circuit of claim 1 , further comprising a level shifter having an input terminal for receiving an input signal, a first output terminal for providing a level shifted input signal, the first output terminal coupled to an input terminal of a first inverter of the first plurality of series-connected inverters, and a second output terminal coupled to an input terminal of a first inverter of the second plurality of series-connected inverters.
6. A driver circuit comprising:
a first plurality of series-connected inverters, each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter, wherein each inverter of the first plurality of series-connected inverters has a first power supply terminal coupled to receive a first power supply voltage, and a second power supply terminal coupled to receive a second power supply voltage regulated to a predetermined voltage level above ground;
a second plurality of series-connected inverters, each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input of a subsequent inverter, the second plurality of series-connected inverters having a same number of inverters as the first plurality of series-connected inverters;
a first transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the output terminal of a last inverter in the first plurality of series-connected inverters, and a second current electrode coupled to an output terminal;
a second transistor having a first current electrode coupled to the output terminal, a control electrode coupled to the output terminal of a last inverter in the second plurality of series-connected inverters, and a second current electrode coupled to a third power supply terminal;
a plurality of capacitors, each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters; and
a first discharge circuit coupled between the second power supply terminal and ground, the first discharge circuit for discharging the second power supply terminal of the first plurality of series-connected inverters in response to a transition of an input signal of the driver circuit from a first logic level to a second logic level.
7. The driver circuit of claim 6 , further comprising a second discharge circuit coupled between the second power supply terminal and ground, the second discharge circuit for discharging the second power supply terminal of the first plurality of series-connected inverters in response to a transition of the input signal of the driver circuit from the second logic level to the first logic level.
8. The driver circuit of claim 7 , wherein the first and second discharge circuits discharge the second power supply terminal of the first plurality of series-connected inverters for a predetermined time period.
9. The driver circuit of claim 6 , further comprising a level shifter having an input terminal for receiving the input signal, a first output terminal for providing a level shifted input signal, the first output terminal coupled to an input terminal of a first inverter of the first plurality of series-connected inverters, and a second output terminal coupled to an input terminal of a first inverter of the second plurality of series-connected inverters.
10. The driver circuit of claim 6 , wherein the first discharge circuit comprises:
a third transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode coupled to receive a first signal based on the input signal, and a second current electrode;
a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive a second signal based on the input signal, and a second current electrode, the second signal having a longer delay than the first signal; and
a current source having a first terminal coupled to the second current electrode of the fourth transistor, and a second terminal coupled to ground.
11. The driver circuit of claim 6 , wherein the plurality of capacitors comprises a plurality of metal plate capacitors.
12. The driver circuit of claim 6 , wherein the second plurality of series-connected inverters receives a third power supply voltage different from the first power supply voltage.
13. The driver circuit of claim 6 , wherein each inverter of the second plurality of series-connected inverters has a first power supply terminal coupled to receive a third power supply voltage, and a second power supply voltage terminal coupled to ground, wherein the third power supply voltage is lower than the first power supply voltage.
14. A driver circuit comprising:
a first plurality of series-connected inverters, each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input terminal of a subsequent inverter, wherein each inverter of the first plurality of series-connected inverters has a first power supply terminal coupled to receive a first power supply voltage, and a second power supply terminal coupled to receive a second power supply voltage regulated to a predetermined voltage level above ground;
a second plurality of series-connected inverters, each inverter having an input terminal and an output terminal, the output terminal of one inverter coupled to an input of a subsequent inverter, the second plurality of series-connected inverters having a same number of inverters as the first plurality of series-connected inverters;
a first transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the output terminal of a last inverter in the first plurality of series-connected inverters, and a second current electrode coupled to an output terminal;
a second transistor having a first current electrode coupled to the output terminal, a control electrode coupled to the output terminal of a last inverter in the second plurality of series-connected inverters, and a second current electrode coupled to a third power supply terminal; and
a plurality of discharge circuits, each discharge circuit of the plurality of discharge circuits coupled between the second power supply terminal and ground, the plurality of discharge circuits for discharging the second power supply terminal of the plurality of series-connected inverters in response to a transition of an input signal of the driver circuit from a first logic level to a second logic level.
15. The driver circuit of claim 14 , wherein each discharge circuit of the plurality of discharge circuits comprising a transistor, wherein the transistor is coupled between the second power supply terminal and ground, and wherein the transistor having a control electrode coupled to receive a control signal.
16. The driver circuit of claim 15 , further comprising a pulse control circuit, the pulse control circuit for providing a plurality of delay signals, a delay signal of the plurality of delay signals being provided to the control electrode of the transistor of the plurality of discharge circuits, wherein the pulse control circuit causing the plurality of discharge circuits to become conductive one at time in a staggered manner.
17. The driver circuit of claim 16 further comprising a replica delay path coupled to the pulse control circuit, the replica delay path for matching a propagation delay of the first plurality of series-connected inverters, and for providing the plurality of delay signals.
18. The driver circuit of claim 14 further comprising a level shifter having an input terminal for receiving an input signal, a first output terminal for providing a level shifted input signal, the first output terminal coupled to an input terminal of a first inverter of the first plurality of series-connected inverters, and a second output terminal coupled to an input terminal of a first inverter of the second plurality of series-connected inverters.
19. The driver circuit of claim 14 wherein the plurality of discharge circuits comprising a first discharge circuit and a second discharge circuit, the first discharge circuit coupled between the second power supply terminal and ground of a first inverter of the first plurality of series-connected inverters, and a second inverter coupled to a last inverter of the first plurality of series-connected inverters, and the driver circuit further comprising a plurality of capacitors, each capacitor of the plurality of capacitors coupled between the output terminals of corresponding inverters of the first and second pluralities of series-connected inverters.