IP Library Granted Patent US 9,645,765
Granted Patent B2
US 9,645,765 · App. 14/728,992 · Granted May 9, 2017

Reading and writing data at multiple, individual non-volatile memory portions in response to data transfer sent to single relative memory address

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,645,765
App. No.
14/728,992
Granted
May 9, 2017
Kind
B2
Abstract

A first memory portion of a plurality of memory portions is configured to determine a designated position of the first memory portion (in a predefined sequence of the plurality of memory portions), and to receive a sub-request conveyed to the plurality of memory portions in the first memory device. The sub-request has a single contiguous instruction portion and a plurality of data segments. The single contiguous instruction portion has a single relative memory address and a single set of one or more instructions to write the data segments. The first memory portion detects that the received sub-request includes an instruction to write data, and in response, identifies a first data segment allocated to the first memory portion, places the first data segment into a buffer of the first memory portion, and writes the buffered first data segment to a location in non-volatile memory of the first memory portion.

Claims (48)

1. A method of performing memory operations in a storage system, the storage system having one or more memory controllers and a set of memory devices, each memory device comprising a plurality of memory portions, the method comprising:

at a first memory portion of the plurality of memory portions in a first memory device of the set of memory devices:

determining a designated position of the first memory portion;

receiving a sub-request conveyed to the plurality of memory portions in the first memory device, wherein the sub-request comprises a single contiguous instruction portion and a plurality of data segments of a data packet, and wherein the single contiguous instruction portion comprises a single relative memory address and a single set of one or more instructions to write the plurality of data segments;

detecting that the received sub-request includes an instruction to write data; and

in response to detecting the instruction to write data:

identifying, of the plurality of data segments, a first data segment allocated to the first memory portion;

placing the first data segment into a buffer of the first memory portion; and

writing the buffered first data segment to a location in non-volatile memory of the first memory portion, the location corresponding to the single relative memory address.

2. The method of claim 1 , wherein each data segment comprises one or more pages of data.

3. The method of claim 1 , wherein each data segment has a size equal to a non-integer multiple of the size of a page of data.

4. The method of claim 3 , wherein the sub-request further comprises memory portion markers positioned between neighboring data segments, and wherein identifying the first data segment includes detecting receipt of a memory portion marker.

5. The method of claim 1 , wherein writing the buffered first data segment includes:

determining if a first location in non-volatile memory of the first memory portion, identified in accordance with the relative memory address, includes one or more bad memory sub-portions; and

in accordance with a determination that the first location includes one or more bad memory sub-portions, writing the buffered first data segment to a second location in non-volatile memory of the first memory portion, the second location corresponding to a remapping of the first location.

6. The method of claim 1 , wherein the single relative memory address identifies a page in each memory portion of the plurality of memory portions.

7. The method of claim 1 , wherein the first memory portion corresponds to a single die.

8. The method of claim 1 , wherein the single relative memory address of the sub-request does not include distinct memory addresses for each memory portion of the first memory device.

9. A storage system, comprising:

a storage device that includes a set of memory devices, a first memory device of the set of memory devices comprising a plurality of memory portions; the storage device further including one or more memory controllers for controlling operation of the storage system and responding to host commands;

wherein a first memory portion of the plurality of memory portions in the first memory device is configured to perform memory operations, including:

determining a designated position of the first memory portion within the first memory device;

receiving a sub-request conveyed to the plurality of memory portions in the first memory device, wherein the sub-request comprises a single contiguous instruction portion and a plurality of data segments of a data packet, and the single contiguous instruction portion comprises a single relative memory address and a single set of one or more instructions to write the plurality of data segments;

detecting that the received sub-request includes an instruction to write data; and

in response to detecting the instruction to write data:

identifying, of the plurality of data segments, a first data segment allocated to the first memory portion;

placing the first data segment into a buffer of the first memory portion; and

writing the buffered first data segment to a location in non-volatile memory of the first memory portion, the location corresponding to the single relative memory address.

10. The storage system of claim 9 , wherein the first memory device includes read/write circuitry for selecting the location in non-volatile memory of the first memory portion, the location corresponding to the single relative memory address, and for causing performance of a write operation to write the buffered first data segment to the selected location in non-volatile memory of the first memory portion.

11. The storage system of claim 9 , wherein the storage device includes read/write circuitry for selecting the location in non-volatile memory of the first memory portion, the location corresponding to the single relative memory address, and for causing performance of a write operation to write the buffered first data segment to the selected location in non-volatile memory of the first memory portion.

12. The storage system of claim 9 , wherein each data segment comprises one or more pages of data.

13. The storage system of claim 9 , wherein each data segment has a size equal to a non-integer multiple of the size of a page of data.

14. The storage system of claim 13 , wherein the sub-request further comprises memory portion markers positioned between neighboring data segments, and wherein identifying the first data segment includes detecting receipt of a memory portion marker.

15. The storage system of claim 9 , wherein writing the buffered first data segment includes:

determining if a first location in non-volatile memory of the first memory portion, identified in accordance with the relative memory address, includes one or more bad memory sub-portions; and

in accordance with a determination that the first location includes one or more bad memory sub-portions, writing the buffered first data segment to a second location in non-volatile memory of the first memory portion, the second location corresponding to a remapping of the first location.

16. The storage system of claim 9 , wherein the single relative memory address identifies a page in each memory portion of the plurality of memory portions.

17. The storage system of claim 9 , wherein the first memory portion corresponds to a single die.

18. The storage system of claim 9 , wherein the single relative memory address of the sub-request does not include distinct memory addresses for each memory portion of the first memory device.

19. A non-transitory computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which, when executed by a local controller, comprising one or more processors and/or state machines, cause a first memory portion of a plurality of memory portions in a first memory device to:

determine a designated position of the first memory portion;

receive a sub-request conveyed to the plurality of memory portions in the first memory device, wherein the sub-request comprises a single contiguous instruction portion and a plurality of data segments of a data packet, and wherein the single contiguous instruction portion comprises a single relative memory address and a single set of one or more instructions to write the plurality of data segments;

detect that the received sub-request includes an instruction to write data; and

in response to detecting the instruction to write data:

identify, of the plurality of data segments, a first data segment allocated to the first memory portion;

place the first data segment into a buffer of the first memory portion; and

write the buffered first data segment to a location in non-volatile memory of the first memory portion, the location corresponding to the single relative memory address.

20. The non-transitory computer readable storage medium of claim 19 , wherein each data segment comprises one or more pages of data.

Assignments (3)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →