BATTERY SYSTEM RESET SYSTEMS AND RELATED METHODS
A battery reset system. Implementations may include: an embedded battery, a battery control circuit coupled with the embedded battery, a discharging field effect transistor (FET) coupled with the battery control circuit, and a charging FET coupled with the battery control circuit. The system may also include a positive battery terminal coupled with the battery and a negative battery terminal coupled with the embedded battery and a reset terminal coupled with a reset circuit coupled with the battery control circuit. The reset circuit and the battery control circuit may be included in a single semiconductor chip coupled with the discharging FET, charging FET, and embedded battery.
1 . An embedded battery system comprising:
an embedded battery;
a battery control circuit coupled with the embedded battery;
a discharging field effect transistor (FET) coupled with the battery control circuit;
a charging FET coupled with the battery control circuit;
a positive battery terminal coupled with the battery and a negative battery terminal coupled with the embedded battery;
a reset terminal coupled with a reset circuit coupled with the battery control circuit;
wherein the reset circuit and battery control circuit are comprised in a single semiconductor chip coupled with the discharging FET, charging FET, and embedded battery.
2 . The system of claim 1 , wherein no other FETs are included except the discharging FET and charging FET.
3 . The system of claim 1 , wherein the reset circuit is configured to turn off at least the discharging FET in response to receiving a reset signal from the reset terminal.
4 . The system of claim 3 , wherein a hardware switch configured to be pressed by a user is coupled with the reset terminal and configured to send a reset signal to the reset circuit when pressed by the user for a predetermined period of time.
5 . The system of claim 3 , wherein the reset circuit is configured to receive a reset signal via the reset terminal from one of a load and a charger coupled to the battery.
6 . The system of claim 3 , wherein the reset circuit is configured to receive a reset signal via the reset terminal when an external power signal is applied to the reset terminal.
7 . The system of claim 6 , wherein the external power signal is sent from a power module integrated circuit (IC) coupled with the positive battery terminal and the negative battery terminal and wherein the reset circuit is configured to test the operation of the embedded battery through turning off at least the discharging FET.
8 . The system of claim 1 , further comprising a test switch and a reset switch, wherein when the test switch is closed, the reset terminal is configured to allow a testing system to test the embedded battery system, and when the reset switch is closed, the reset terminal is configured to receive reset signals and forward them to the reset circuit.
9 . The system of claim 8 , wherein the test switch is configured to close in response to receiving one of a testing current sense signal, a testing voltage signal and both a testing current sense signal and a testing voltage signal at the positive battery terminal wherein one of the testing current sense signal and the testing voltage signal are configured to be above an overcharge voltage level for the embedded battery.
10 . The system of claim 1 , further comprising:
a fuse array;
a reset logic circuit configured to turn off at least the discharging FET in response to receiving a reset signal from the reset terminal;
at least one testing fuse coupled with the fuse array and reset logic circuit and configured to move a test/reset switch from a testing position to a reset position upon receiving a testing fuse trimming signal and an end of a testing sequence of the embedded battery system.
11 . A battery control system for an embedded battery, the system comprising:
a battery control circuit configured to be coupled with an embedded battery;
a discharging field effect transistor (FET) coupled with the battery control circuit;
a charging FET coupled with the battery control circuit;
a positive battery terminal coupled with the battery and a negative battery terminal coupled with the battery control circuit;
a reset terminal coupled with a reset circuit coupled with the battery control circuit;
wherein the reset circuit and battery control circuit are comprised in a single semiconductor chip coupled with the discharging FET and charging FET.
12 . The system of claim 11 , wherein no other FETs are included except the discharging FET and charging FET.
13 . The system of claim 11 , wherein the reset circuit is configured to turn off at least the discharging FET in response to receiving a reset signal from the reset terminal.
14 . The system of claim 13 , wherein a hardware switch configured to be pressed by a user is coupled with the reset terminal and configured to send a reset signal to the reset circuit when pressed by the user for a predetermined period of time.
15 . The system of claim 13 , wherein the reset circuit is configured to receive a reset signal via the reset terminal from a one of a load and a charger coupled to the battery control circuit.
16 . The system of claim 13 , wherein the reset circuit is configured to receive a reset signal via the reset terminal when an external power signal is applied to the reset terminal.
17 . The system of claim 16 , wherein the external power signal is sent from a power module integrated circuit (IC) coupled with the positive battery terminal and the negative battery terminal and wherein the reset circuit is configured to test the operation of the embedded battery through turning off at least the discharging FET.
18 . The system of claim 11 , further comprising a test switch and a reset switch, wherein when the test switch is closed, the reset terminal is configured to allow a testing system to test the embedded battery system, and when the reset switch is closed, the reset terminal is configured to receive reset signals and forward them to the reset circuit.
19 . The system of claim 18 , wherein the test switch is configured to close in response to receiving one of a testing current sense signal, a testing voltage signal and both a testing current sense signal and a testing voltage signal at the positive battery terminal wherein one of the testing current sense signal and the testing voltage signal are configured to be above an overcharge voltage level for the embedded battery.
20 . The system of claim 11 , further comprising:
a fuse array;
a reset logic circuit configured to turn off at least the discharging FET in response to receiving a reset signal from the reset terminal;
at least one testing fuse coupled with the fuse array and reset logic circuit and configured to move a test/reset switch from a testing position to a reset position upon receiving a testing fuse trimming signal and an end of a testing sequence of the embedded battery system.