Power-down discharger
Active post-power loss discharging of capacitors is provided. In an integrated circuit having a startup behavior depending on a capacitor voltage, a discharge transistor is provided to discharge the capacitor. A power-down discharger actively drives the discharge transistor after a power supply voltage drops below a threshold. The power-down discharger may include, or be coupled to, an internal capacitance that is charged when the power supply voltage is above the threshold, thereby storing sufficient energy for later driving of the discharge transistor. A diode is employed to ensure that the loss of power does not drain away the needed energy until after the discharge has been completed. One illustrative discharging method includes: sensing a condition indicative of power supply voltage loss for an integrated circuit; and actively driving the discharge transistor into a conducting state. The sensing may include driving the discharge transistor inversely to a signal from a pin.
1. A low dropout (LDO) regulator that comprises:
an output transistor that couples a DC input voltage pin to a DC output voltage pin;
an operational amplifier that drives the output transistor in response to a difference between a feedback signal and a reference voltage from a capacitor;
a soft-start circuit that ramps the reference voltage from an initial voltage;
a discharge transistor that discharges the capacitor when driven to a conducting state; and
a power-down discharger that includes:
an internal capacitance;
a diode, or transistor configured as a diode, connecting the DC input voltage pin to the internal capacitance to charge the internal capacitance;
a sense transistor connecting the internal capacitance to a gate of the discharge transistor to drive the discharge transistor to the conducting state when a voltage on the DC input voltage pin drops below a threshold.
2. The low dropout (LDO) regulator of claim 1 , wherein the discharge transistor is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS), and the sense transistor is a p-channel metal-oxide-semiconductor field-effect transistor (PMOS) having a gate connected to the DC input voltage pin.
3. An integrated power switch that comprises:
an output transistor that couples a power supply voltage on a DC input voltage pin to a DC output voltage pin;
a high-impedance source that drives a gate of the output transistor;
a discharge transistor that discharges the gate of the output transistor when driven to a conducting state; and
a power-down discharger that includes:
a sense transistor having a gate that receives an enable signal;
a diode, or transistor configured as a diode, connecting the sense transistor to a gate of the discharge transistor to drive the discharge transistor to the conducting state when the enable signal is de-asserted.
4. The integrated power switch of claim 3 , wherein the power-down discharger further includes an internal capacitance connected to the gate of the discharge transistor.
5. The integrated power switch of claim 3 , wherein the discharge transistor is an n-channel metal-oxide-semiconductor field-effect transistor (NMOS), and the sense transistor is a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).