Matrix lid heatspreader for flip chip package

1. A semiconductor package, comprising:

a substrate having first and second surfaces;

a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;

a compressed, laterally expansive, thermally conductive interface layer formed to cover the second surface of the die; and

a heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the compressed, laterally expansive, thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid, wherein

the heat spreader lid comprises an etched, machined, or stamped metal layer defining an upset heat spreader lid having a plurality of downset lead finger spars to define one or more singulation cut area openings around the heat spreader lid.

2. The semiconductor package of claim 1 , where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.

3. The semiconductor package of claim 1 , where the heat spreader lid is formed with a thermally conductive layer of copper, nickel or an alloy thereof.

4. The semiconductor package of claim 1 , where the exposed heat dissipation surface layer has a thermal contact surface that is at least as large as the second surface of the die.

5. The semiconductor package of claim 1 , further comprising an array of solder balls attached to the second surface of the substrate to make electrical connection to the die via conductive traces formed in the substrate.

6. The semiconductor package of claim 1 , where the plurality of connection spars are embedded and surrounded by the encapsulation mold compound material except at peripheral side ends of the semiconductor package.

7. A semiconductor device, comprising:

a substrate array;

a plurality of integrated circuit die attached to the substrate array, each integrated circuit die having a first surface that is attached to a first surface of the substrate array using flip chip bumps and a second, opposed surface;

a plurality of compressed thermally conductive interface layers attached, respectively, to each second, opposed surface of each integrated circuit die;

a heat spreader lid array comprising a plurality of heat spreader lids having planar upper lid surfaces connected together by connection spars to define one or more singulation cut area openings around each head spreader lid, the heat spreader lid array attached to the plurality of compressed thermally conductive interface layers to form a compressed thermally conductive interface layer which completely covers each second, opposed surface of each integrated circuit die to provide direct contact between each integrated circuit die and the heat spreader lid array, wherein

the heat spreader lid array comprises an etched, machined, or stamped metal layer defining a plurality of upset heat spreader lids connected together by a plurality of downset lead finger spars to define the one or more openings between adjacent heat spreader lids; and

a mold compound package encapsulating the plurality of integrated circuit die and the heat spreader lid array except for the planar upper lid surfaces of the plurality of heat spreader lids which are exposed through the mold compound package.

8. The semiconductor device of claim 7 , further comprising a ball grid array attached to an exposed surface of said substrate array for electrical connection through the substrate array to the plurality of integrated circuit die.

9. The semiconductor device of claim 7 , where the plurality of compressed thermally conductive interface layers comprises a thermally conductive, compliant adhesive layer that is applied to each second, opposed surface of each integrated circuit die.

10. The semiconductor device of claim 7 , where the plurality of compressed thermally conductive interface layers comprises a patterned layer of compliant, thermally conductive grease that is applied to each second, opposed surface of each integrated circuit die.

11. The semiconductor device of claim 7 , where the plurality of compressed thermally conductive interface layers comprises a patterned layer of compliant, thermally conductive non-curing silicon material that is applied to each second, opposed surface of each integrated circuit die.

12. A semiconductor package, comprising:

a substrate array;

a plurality of integrated circuit die attached to the substrate array, each integrated circuit die having a first surface that is attached to the substrate array and a second, opposed surface;

a plurality of compressed and compliant thermally conductive interface layers completely covering, respectively, each second, opposed surface of each integrated circuit die; and

a heat spreader lid array comprising a plurality of heat spreader lids connected together by connection spars, where a bottom surface of each heat spreader lid makes direct contact to the plurality of compressed and compliant thermally conductive interface layers, wherein

the heat spreader lid array comprises an etched, machined, or stamped metal layer defining the plurality of heat spreader lids which are connected together by a plurality of downset lead finger spars to define one or more openings between adjacent heat spreader lids.

13. The semiconductor package of claim 12 , further comprising a mold compound package encapsulating the plurality of integrated circuit die and the heat spreader lid array except for a planar upper surface of each heat spreader lid which remains exposed through the mold compound package.

14. The semiconductor package of claim 12 , where the plurality of integrated circuit die are attached to the substrate array using flip-chip bonding to enable electrical connection between each integrated circuit die and conductors in the substrate array.

15. The semiconductor package of claim 12 , where the heat spreader lid array comprises an unlaminated thermally conductive material defining the plurality of heat spreader lids positioned for alignment with the plurality of integrated circuit die, where each heat spread lid comprises an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the exposed heat dissipation surface layer.