IP Library Granted Patent US 9,456,159
Granted Patent B1
US 9,456,159 · App. 14/862,830 · Granted Sep 27, 2016

Pixels with an active reset circuit in CMOS image sensors

Inventor: Jaroslav Hynecek (Allen, TX)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/37457H01L27/14609H04N5/363H04N5/378
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,456,159
App. No.
14/862,830
Granted
Sep 27, 2016
Kind
B1
Abstract

The invention disclosure describes pixels arranged into CMOS image sensor arrays that may be back side illuminated and may operate in a global shutter mode. The image sensor pixels may also be front side illuminated. The pixel charge storage sites for the global shutter operation are formed by floating diffusions that are small and do not collect a significant number of stray charge, which contributes to the sensor's high shutter efficiency. The floating diffusions are reset by an active reset circuit that significantly reduces generation of kTC reset noise. The active reset circuit consists of an in-pixel inverting amplifier formed by a p-channel gain transistor with an n-channel transistor load, and a feedback reset transistor connected from the amplifier output to the amplifier input, which is the FD node. The active reset circuit does not utilize a significant portion of the pixel area and has low power consumption.

Claims (32)

1. An image sensor having a pixel array that includes an array of pixels, wherein a pixel of the array of pixels comprises:

a floating diffusion region;

a photodiode that is coupled to the floating diffusion region;

a charge transfer transistor coupled between the photodiode and the floating diffusion region; and

an active reset circuit that includes an inverting amplifier, wherein the inverting amplifier comprises a p-channel gain transistor and an n-channel load transistor, and wherein the active reset circuit further comprises a reset transistor coupled between an output of the inverting amplifier and the floating diffusion region.

2. The image sensor defined in claim 1 , wherein the pixel further comprises a source follower transistor.

3. The image sensor defined in claim 2 , wherein the source follower transistor is coupled to the floating diffusion region.

4. The image sensor defined in claim 2 , wherein the pixel further comprises a pixel addressing transistor.

5. The image sensor defined in claim 1 , wherein the pixel is a back-side illuminated pixel.

6. The image sensor defined in claim 5 , wherein the photodiode is formed in a substrate, the pixel further comprising a color filter and a microlens formed on a back side of the substrate.

7. The image sensor defined in claim 1 , wherein the pixel is a front-side illuminated pixel.

8. The image sensor defined in claim 7 , wherein the photodiode is formed in a substrate, the pixel further comprising a color filter and a microlens formed on a front side of the substrate.

9. The image sensor defined in claim 1 , wherein the active reset circuit is configured to reset the floating diffusion region to a reference voltage.

10. The image sensor defined in claim 9 , wherein the inverting amplifier is configured to be turned off after the floating diffusion region is reset to the reference voltage.

11. The image sensor defined in claim 9 , wherein the p-channel gain transistor is configured to amplify a signal from the floating diffusion region after the floating diffusion region is reset to the reference voltage.

12. An imaging pixel comprising:

a floating diffusion region; and

an active reset circuit that includes an inverting amplifier, wherein the inverting amplifier comprises a p-channel gain transistor and an n-channel load transistor, and wherein the active reset circuit further comprises a reset transistor coupled between an output of the inverting amplifier and the floating diffusion region.

13. The imaging pixel defined in claim 12 , wherein the active reset circuit is configured to reset the floating diffusion region to a reference voltage.

14. The imaging pixel defined in claim 13 , wherein the p-channel gain transistor is configured to amplify a signal from the floating diffusion region after the floating diffusion region is reset to the reference voltage.

15. The image sensor defined in claim 12 , wherein the pixel further comprises a source follower transistor.

16. The image sensor defined in claim 15 , wherein the source follower transistor is coupled to the floating diffusion region.

17. The image sensor defined in claim 16 , wherein the pixel further comprises a pixel addressing transistor.

18. A system, comprising:

a central processing unit;

memory;

a lens;

input-output circuitry; and

an imaging device, wherein the imaging device comprises:

an array of pixels, each of which includes a floating diffusion region and an active reset circuit that includes an inverting amplifier, wherein the inverting amplifier comprises a p-channel gain transistor and an n-channel load transistor, and wherein the active reset circuit further comprises a reset transistor coupled between an output of the inverting amplifier and the floating diffusion region.

19. The system defined in claim 18 , wherein each pixel of the array of pixels includes a source follower transistor.

20. The system defined in claim 19 , wherein each pixel of the array of pixels includes a pixel addressing transistor.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2015
From: HYNECEK, JAROSLAV
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 036637/0103 →