Oscillator circuit and method of generating a clock signal
View Patent ↗An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.
1. An oscillator circuit for providing a clock signal, the oscillator circuit comprising:
a comparator;
a varying voltage source and a voltage reference arranged to carry a reference voltage for connection to first and second inputs of the comparator respectively, wherein the comparator is arranged to compare a varying voltage source with a reference voltage; and
a control device arranged to periodically reverse the inputs to the comparator.
2. The oscillator circuit of claim 1 for providing a clock signal, the oscillator circuit comprising:
first and second comparators;
a first varying voltage source and a first voltage reference arranged to carry a first reference voltage for connection to first and second inputs respectively of the first comparator;
a second varying voltage source and a second voltage reference arranged to carry a second reference voltage for connection to first and second inputs respectively of the second comparator, wherein each comparator is arranged to provide first and second comparator signals respectively from comparing a varying voltage with a reference voltage;
a flip-flop arranged to set an output thereof in response to a signal from the first comparator and to reset said output in response to a signal from the second comparator, thereby producing a clock signal at said output of the flip-flop;
a first control device arranged to reverse the inputs of the first comparator when the flip-flop is set; and
a second control device for reversing the inputs of the second comparator when the flip-flop is reset.
3. The oscillator circuit of claim 2 , wherein
the first and second reference voltages are equal,
the first varying voltage source comprises a first current source, a first capacitor and a first switch,
the second varying voltage source comprises a second current source, a second capacitor and a second switch,
said first switch being arranged to enable charging of the first capacitor by the first current source while the output of the flip-flop is at a first logic level and discharging of the first capacitor while the output of the flip-flop is at a second logic level which is the inverse of the first logic level, and
said second switch is arranged to enable charging of the second capacitor by the second current source while the output of the flip-flop is at a second logic level which is the inverse of the first logic level and discharging of the second capacitor while the output of the flip-flop is at the first logic level.
4. The oscillator circuit of claim 2 , wherein
the first and second reference voltages have different values,
the first varying voltage source comprises a first current source, a capacitor and a first switch and the second varying current source comprises a second current source, said capacitor and a second switch, and
the first switch is arranged to enable charging of the capacitor by the first current source while the output of the flip-flop is at a first logic level and the second switch is arranged to permit charging of the capacitor by the second current source while the output of flip-flop is at a second logic level which is the inverse of the first logic level.
5. The oscillator circuit of claim 1 wherein
the first control device comprises a first divide-by-two module and a first switching module wherein the first divide-by-two module has an input operably coupled to the output of the flip-flop and an output operably coupled to the first switching module, the first switching module being arranged to reverse the inputs to the first comparator whenever the output from the first divide-by-two module changes state, and
the second control device comprises a second divide-by-two module and a second switching module wherein the second divide-by-two module has an input operably coupled to an inverse output of the flip-flop and an output operably coupled to the second switching module, the second switching module being arranged to reverse the inputs to the second comparator whenever the output from the second divide-by-two module changes state.
6. The oscillator circuit of claim 5 wherein the first and second divide-by-two modules comprise first and second flip-flops.
7. The oscillator circuit of claim 1 and comprising a polarity adjustment module operably coupled between an output of the comparator and the flip-flop and arranged to adjust the polarity of an output of the comparator.
8. The oscillator circuit of claim 7 wherein a polarity adjustment module comprises an exclusive-or gate having a first input operably coupled to a comparator and a second input operably coupled to a control signal whose state changes every other time the flip flop's output state changes.
9. The oscillator circuit of claim 1 wherein the oscillator circuit is implemented in an integrated circuit.
10. A method for generating a clock signal in an oscillator circuit comprising a comparator, the method comprising:
applying a varying voltage to one input of the comparator and a reference voltage to another input of the comparator;
comparing a varying voltage with a reference voltage; and
periodically reversing the inputs to the comparator.
11. The method of claim 10 for generating a clock signal in an oscillator circuit comprising first and second comparators and a flip-flop, the method comprising:
applying a varying voltage and a reference voltage to first and second inputs respectively of each of the first and second comparators;
applying an output of each of the first and second comparators to the flip-flop, in each first and second comparator;
comparing a varying voltage with a reference voltage to produce first and second comparator signals respectively; and
in the flip-flop, setting an output thereof in response to a first comparator signal and resetting said output in response to a second comparator signal, thereby producing a clock signal at an output of the flip-flop, and reversing the inputs of the first comparator when the flip-flop is set, and reversing the inputs of the second comparator when the flip-flop is reset.