IP Library Granted Patent US 9,455,225
Granted Patent B2
US 9,455,225 · App. 14/918,788 · Granted Sep 27, 2016

Semiconductor device

Inventor: Kiyotada Funane (Itami, JP)
Assignee: Renesas Electronics Corporation
H01L23/5283G11C5/063G11C5/14G11C11/417H01L23/481H01L23/5226H01L23/5286H01L27/11H01L27/1104H01L27/1116H01L23/528H01L27/0207H01L2924/0002
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Quick Facts
Patent No.
US 9,455,225
App. No.
14/918,788
Granted
Sep 27, 2016
Kind
B2
Abstract

To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

Claims (17)

1. A semiconductor device, comprising:

a first wiring which extends in a first direction and is arranged in a first wiring layer;

a second wiring which extends in a second direction perpendicular to the first direction, and is arranged in a second wiring layer to intersect with the first wiring;

a first projecting portion which is integrally formed with the first wiring to project in the second direction from the first wiring;

a plurality of first vias which are arranged in the second direction and electrically couple the second wiring to the first wiring, at least one of the first vias disposed over the first projection portion;

a third wiring which extends in the first direction and is arranged in the first wiring layer;

a fourth wiring which extends in the second direction and is arranged in the second wiring layer to intersect with the first and third wirings;

a second projecting portion which is integrally formed with the third wiring to project in the second direction from the third wiring, the first and second projecting portions both disposed between the first and third wirings; and

a plurality of second vias which are arranged in the second direction and electrically couple the fourth wiring to the third wiring, at least one of the second vias disposed over the second projection portion.

2. The semiconductor device according to claim 1 ,

wherein the first and third wirings are power supply voltage lines which have different voltages each other.

3. The semiconductor device according to claim 1 , further comprising;

a fifth wiring which is arranged in the first wiring between the first and third wirings and is shorter than the first and third wirings in the first direction.

4. The semiconductor device according to claim 3 ,

wherein the fifth wiring is a power supply voltage line having a voltage higher than that of the fifth wiring.

5. The semiconductor device according to claim 1 , wherein the first to fourth wirings, the

first and second projection portions, and the plurality of first and second vias are incorporated with a Static Random Access Memory (SRAM).

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044533/0739 →
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2012-037968 · Feb 23, 2012 · national
Continuity (3)
Division 14471278 · Aug 28, 2014
Continuation 13774453 · Feb 22, 2013
Related Publication 20160049368A1 · Feb 18, 2016