Electromigration-aware integrated circuit design methods and systems
View Patent ↗Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.
1. A method comprising:
accessing technology files for a specific technology node, design specifications for a design for an integrated circuit in the specific technology node, and library files for library elements in the design;
defining protected zones around at least some of the library elements in the design, using the technology files, the design specifications, and the library files, the protected zones around at least two different library elements having different sizes; and,
establishing placement of the library elements in the design relative to power rails in a power delivery network such that each library element is prevented from being placed in a protected zone around any other library element in order to avoid electromigration fails in the power delivery network.
2. The method of claim 1 , the method further comprising, before the defining of the protected zones, performing power planning to define a power delivery network comprising power rails and the defining of the protected zones comprising:
for a net in the design, using the technology files, the design specifications and the library files to determine values for multiple variables, the multiple variables comprising: an electromigration current limit; an activity factor; switching frequency; voltage; overlap capacitance; leakage power; dynamic power based on the activity factor, the switching frequency, the voltage and the overlap capacitance; total power amount based on the leakage power and the dynamic power, and maximum current carrying capacity of the power rails based on the electromigration current limit; and,
for each one of the library elements in the net, determining a current consumption amount that is based on the total power amount and a ratio of the current consumption amount to the maximum current carrying capacity, wherein the protected zones are defined around any of the library elements having current consumption to maximum current carrying capacity ratios that are greater than a predetermined threshold ratio.
3. The method of claim 2 , further comprising, when the maximum current carrying capacity is less than a product of the current consumption amount and the ratio of the current consumption amount to the maximum current carrying capacity for any of the library elements, repeating the performing of the power planning before defining the protected zones.
4. The method of claim 2 , the different sizes depending upon the current consumption to maximum current carrying capacity ratios of the different library elements.
5. The method of claim 2 , further comprising, after the establishing of the placement of the library elements, synthesizing a clock distribution network for the integrated circuit, the synthesizing being performed using the multiple variables to avoid additional electromigration fails in the clock distribution network.
6. The method of claim 5 , further comprising:
before the performing of the power planning, performing floorplanning;
after the performing of the power planning, performing input/output pin placement;
after the synthesizing of the clock distribution network, performing the following processes: a wire routing process, a timing and signal integrity verification process, a physical verification process, and an electromigration and voltage drop verification process; and,
when the design fails the electromigration and voltage drop verification process, adjusting design rules used to define the protected zones and reworking the design starting with redesigning the power delivery network.
7. The method of claim 1 , the library files containing timing information for the library elements and the placement of the library elements being established based on the library files such that the placement of the library elements is also timing optimized.
8. A system comprising:
a memory storing technology files for a specific technology node, design specifications for a design for an integrated circuit in the specific technology node, and library files for library elements in the design; and,
a processor in communication with the memory, the design comprising library elements, and the processor performing the following:
accessing, from the memory, the technology files, the design specifications and the library files;
defining protected zones around at least some of the library elements in the design using the technology files, the design specifications, and the library files, the protected zones around at least two different library elements having different sizes; and
establishing placement of the library elements in the design relative to power rails in a power delivery network such that each library element is prevented from being placed in a protected zone around any other library element in order to avoid electromigration fails in the power delivery network.
9. The system of claim 8 , the processor performing power planning to define a power delivery network comprising power rails prior to defining the protected zones and the processor defining the protected zones by performing the following:
for a net in the design, using the technology files, the design specifications and the library files to determine values for multiple variables, the multiple variables comprising: an electromigration current limit; an activity factor; switching frequency; voltage; overlap capacitance; leakage power; dynamic power based on the activity factor, the switching frequency, the voltage and the overlap capacitance; total power amount based on the leakage power and the dynamic power, and maximum current carrying capacity of the power rails based on the electromigration current limit; and,
for each one of the library elements in the net, determining a current consumption amount that is based on the total power amount and a ratio of the current consumption amount to the maximum current carrying capacity, wherein the protected zones are defined around any of the library elements having current consumption to maximum current carrying capacity ratios that are greater than a predetermined threshold ratio.
10. The system of claim 9 , the processor further repeating the performing of the power planning before defining the protected zones, when the maximum current carrying capacity is less than a product of the current consumption amount and the ratio of the current consumption amount to the maximum current carrying capacity for any of the library elements.
11. The system of claim 9 , the different sizes depending upon the current consumption to maximum current carrying capacity ratios of the different library elements.
12. The system of claim 9 , the processor further synthesizing a clock distribution network for the integrated circuit after the placement of the library elements is established, the synthesizing being performed using the multiple variables to avoid additional electromigration fails in the clock distribution network.
13. The system of claim 12 ,
before the performing of the power planning, the processor performing floorplanning, after the performing of the power planning, the processor performing input/output pin placement, after the synthesizing of the clock distribution network, the processor performing the following processes: a wire routing process, a timing and signal integrity verification process, a physical verification process, and an electromigration and voltage drop verification process; and,
when the design fails the electromigration and voltage drop verification process, the processor adjusting design rules used to define the protected zones and reworking the design starting with redesigning the power delivery network.
14. The system of claim 9 , the library files containing timing information for the library elements and the placement of the library elements being established based on the library files such that the placement of the library elements is also timing optimized.
15. A computer program product for integrated circuit design, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to perform a method, the method comprising:
accessing, from memory, technology files for a specific technology node, design specifications for a design for an integrated circuit in the specific technology node, and library files for library elements in the design;
defining protected zones around at least some of the library elements in the design, using the technology files, the design specifications, and the library files, the protected zones around at least two different library elements having different sizes; and,
establishing placement of the library elements in the design relative to power rails in a power delivery network such that each library element is prevented from being placed in a protected zone around any other library element in order to avoid electromigration fails in the power delivery network.
16. The computer program product of claim 15 , the method further comprising, before the defining of the protected zones, performing power planning to define a power delivery network comprising power rails and the defining of the protected zones comprising:
for a net in the design using the technology files, the design specifications and the library files to determine values for multiple variables, the multiple variables comprising: an electromigration current limit; an activity factor; switching frequency; voltage; overlap capacitance; leakage power; dynamic power based on the activity factor, the switching frequency, the voltage and the overlap capacitance; total power amount based on the leakage power and the dynamic power, and maximum current carrying capacity of the power rails based on the electromigration current limit; and,
for each one of the library elements in the net, determining a current consumption amount that is based on the total power amount and a ratio of the current consumption amount to the maximum current carrying capacity, wherein the protected zones are defined around any of the library elements having current consumption to maximum current carrying capacity ratios that are greater than a predetermined threshold ratio.
17. The computer program product of claim 16 , the method further comprising, after the establishing of the placement of the library elements, synthesizing a clock distribution network for the integrated circuit, the synthesizing being performed using the multiple variables to avoid additional electromigration fails in the clock distribution network.
18. The computer program product of claim 16 , the different sizes depending upon the current consumption to maximum current carrying capacity ratios of the different library elements.
19. The computer program product of claim 16 , the method further comprising synthesizing a clock distribution network for the integrated circuit after the placement of the library elements is established, the synthesizing being performed using the multiple variables to avoid additional electromigration fails in the clock distribution network.
20. The computer program product of claim 19 , the method further comprising:
before the performing of the power planning, performing floorplanning;
after the performing of the power planning, performing input/output pin placement;
after the synthesizing of the clock distribution network, performing the following processes: a wire routing process, a timing and signal integrity verification process, a physical verification process, and an electromigration and voltage drop verification process; and,
when the design fails the electromigration and voltage drop verification process, adjusting design rules used to define the protected zones and reworking the design starting with redesigning the power delivery network.