Enhanced sensitivity ion sensing devices
View Patent ↗A mechanism is provided for enhancing the sensitivity of an ion-sensitive semiconductor device by creating a second gate coupled to a sense plate that can improve the amount of charge brought to the ion-sensitive semiconductor device conductivity modulated region (e.g., a channel region of an ISFET). This is accomplished by utilizing a buried dielectric layer associated with the ion-sensitive semiconductor device conductivity modulated region as the second gate dielectric. The buried dielectric layer is coupled to the sense plate using an isolated well region as a conductor that is coupled to metal layers extending to the sense plate. Some embodiments further use the buried dielectric layer as the sole gate dielectric for the semiconductor device, thereby allowing the traditional gate dielectric region to be coupled to a protection diode. This protection diode then protects the gate dielectric from plasma induced damage and electrostatic discharge.
1. An ion sensitive semiconductor device comprising:
a substrate comprising a surface;
a semiconductor device layer, formed within the surface of the substrate, and comprising a conductivity modulated region, a first doped region disposed laterally adjacent to the conductivity modulated region, and a second doped region disposed laterally adjacent to the conductivity modulated region;
a gate stack formed on the surface of the substrate and over a first surface of the conductivity modulated region;
a buried dielectric layer formed within the substrate and adjacent to a second surface of the conductivity modulated region, wherein the second surface is opposite to the first surface;
a conductive well region formed within the substrate beneath and adjacent to the buried dielectric layer, wherein the conductive well region is electrically isolated from the remainder of the substrate;
multiple conductive structures overlying the surface of the substrate, wherein the multiple conductive structures comprise
a first conductor formed in first metal layer electrically coupled to the conductive well region by a first conductive via, and
an ion-sensitive sense plate structure electrically coupled to the first conductor and configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the ion-sensitive sense plate structure.
2. The ion sensitive semiconductor device of claim 1 further comprising:
a floating gate structure formed over the gate stack, wherein
the gate stack comprises a gate conductor and a gate dielectric,
the floating gate structure comprises a second conductor formed in the first metal layer and is electrically coupled to the gate conductor by a second conductive via, and
the ion-sensitive sense plate is electrically coupled to the second conductor.
3. The ion sensitive semiconductor device of claim 2 wherein the first and second conductors are the same conductor.
4. The ion sensitive semiconductor device of claim 2 wherein the first and second conductors are separate conductors.
5. The ion sensitive semiconductor device of claim 2 wherein the ion sensitive sense plate structure is one of directly electrically coupled to the first and second conductors or capacitively coupled to the first and second conductors.
6. The ion sensitive semiconductor device of claim 1 further comprising:
a protection diode structure formed in the semiconductor device layer and electrically coupled to the substrate; and
a floating gate structure formed over the gate stack, wherein
the gate stack comprises a gate conductor and a gate dielectric,
the floating gate structure comprises a second conductor formed in the first metal layer and is electrically coupled to the gate conductor by a second conductive via, and
the protection diode structure is electrically coupled to the second conductor by a third conductive via.
7. The ion sensitive semiconductor device of claim 6 wherein the ion sensitive sense plate structure is electrically coupled to the first conductor and not electrically coupled to the second conductor.
8. The ion sensitive semiconductor device of claim 6 wherein the ion sensitive sense plate structure is one of directly electrically coupled to the first conductor or capacitively coupled to the first conductor.
9. The ion sensitive semiconductor device of claim 1 , wherein the semiconductor device is an ion sensitive field effect transistor and
the first doped region comprises a dopant of a first conductivity type,
the second doped region comprises a dopant of the first conductivity type,
the conductivity modulated region comprises a dopant of a second conductivity type, and
the conductive well region comprises a dopant of the second conductivity type.
10. The ion sensitive semiconductor device of claim 1 , wherein the semiconductor device is an ion sensitive gated diode and
the first doped region comprises a dopant of a first conductivity type,
the second doped region comprises a dopant of a second conductivity type,
the conductivity modulated region comprises a dopant of the second conductivity type, and
the conductive well region comprises a dopant of the second conductivity type.
11. The ion sensitive semiconductor device of claim 1 , wherein the semiconductor device is an ion sensitive gated lateral bipolar junction transistor, and
the first doped region comprises a dopant of a first conductivity type and is a emitter,
the second doped region comprises a dopant of the first conductivity type and is a collector,
the conductivity modulated region comprises a dopant of a second conductivity type,
the conductive well region comprises a dopant of the second conductivity type, and
the emitter, conductivity modulated region, and collector form concentric regions with the emitter in the center, the conductivity modulated region surrounding the emitter, and the collector surrounding the conductivity modulated region.
12. A method of forming an ion sensitive semiconductor device structure, the method comprising:
forming a first well region of a first conductivity type in a substrate of a second conductivity type;
forming a second well region of a second conductivity type within the first well region;
forming a buried dielectric layer within the second well region;
forming a semiconductor device layer within the substrate, wherein
the semiconductor device layer comprises a conductivity modulated region, a first doped region disposed laterally adjacent to the conductivity modulated region, and a second doped region disposed laterally adjacent to the conductivity modulated region,
the semiconductor device layer is disposed above each of the first well region, the second well region, and the buried dielectric layer, and
the conductivity modulated region is disposed above and adjacent to the buried dielectric layer;
electrically isolating the second doped region from the remainder of the semiconductor device layer by forming a second trench extending from the surface of the semiconductor device layer to a depth within the second well region, but not extending to the first well region; and
electrically coupling the second doped region to an ion-sensitive sense plate structure that is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the ion-sensitive sense plate structure.
13. The method of claim 12 further comprising:
forming a third trench extending from the surface of the semiconductor device layer to a depth within the second well region along a first boundary of the first and second well regions;
forming a fourth trench extending from the surface of the semiconductor device layer to a depth within the second well region along a second boundary of the first and second well regions;
forming a fifth trench extending from the surface of the semiconductor device layer along a first boundary of the first well region with the remainder of the substrate;
forming a sixth trench extending from the surface of the semiconductor device layer along a second boundary of the first well region with the remainder of the substrate; and
forming a dielectric within the first, second, third, fourth, fifth, and sixth trenches.
14. The method of claim 12 wherein said electrically coupling the second doped region to the ion-sensitive sense plate further comprises:
forming a first dielectric layer above and in contact with at least a portion of the semiconductor device layer;
forming a first metal layer above the first dielectric layer, wherein the first metal layer comprises a first conductor;
forming a first conductive via through the first dielectric layer, wherein the first conductive via is configured to electrically couple the first conductor with the second doped region;
forming a second dielectric layer above and in contact with the first metal layer;
forming a second metal layer above the second dielectric layer, wherein the second metal layer comprises a second conductor aligned over the first conductor;
forming a third dielectric layer above and in contact with the second metal layer;
forming an ion-sensitive sense plate above the third dielectric layer; and
forming a second conductive via through the third dielectric layer, wherein
the second conductive via is configured to electrically couple the ion-sensitive sense plate with the second conductor, and
the second conductor is capacitively coupled with the first conductor.
15. The method of claim 14 further comprising:
forming a gate dielectric and a gate over the conductivity modulated region;
forming a third conductor in the first metal layer;
forming a third conductive via through the first dielectric layer, wherein the third conductive via is configured to electrically couple the third conductor with the gate.
16. The method of claim 15 wherein the second metal layer further comprises a fourth conductor, and the method further comprises:
forming a fourth conductive via through the third dielectric layer, wherein
the fourth conductive via is configured to electrically couple the ion-sensitive sense plate with the fourth conductor,
the fourth conductor is aligned over the third conductor, and
the fourth conductor is capacitively coupled with the third conductor.
17. The method of claim 15 further comprising:
forming a protection diode circuit in a portion of the semiconductor device layer;
forming a fifth conductive via through the first dielectric layer, wherein the fifth conductive via is configured to electrically couple the third conductor with the protection diode circuit.
18. The method of claim 12 further comprising:
doping the first doped region with a dopant of a first conductivity type;
doping the second doped region with a dopant of the first conductivity type;
doping the conductivity modulated region with a dopant of a second conductivity type;
doping the second well region with a dopant of the second conductivity type; and
doping first well region with a dopant of the first conductivity type.
19. The method of claim 12 further comprising:
doping the first doped region with a dopant of a first conductivity type;
doping the second doped region with a dopant of a second conductivity type;
doping the conductivity modulated region with a dopant of the second conductivity type;
doping the second well region with a dopant of the second conductivity type; and
doping the first well region with a dopant of the first conductivity type.
20. The method of claim 12 further comprising:
doping the first doped region with a dopant of a first conductivity type and is a emitter;
doping the second doped region with a dopant of the first conductivity type and is a collector;
doping the conductivity modulated region with a dopant of a second conductivity type;
doping the second well region with a dopant of the second conductivity type; and
forming the emitter, conductivity modulated region, and collector as concentric regions with the emitter in the center, the conductivity modulated region surrounding the emitter, and the collector surrounding the conductivity modulated region.