Semiconductor device and structure therefor

1. A HEMI semiconductor device comprising:

a first plurality of via structures overlying a plurality of first current carrying electrodes of the HEMI semiconductor device, the first plurality of via structures having a first via conductor electrically coupled to the plurality of first current carrying electrodes;

a second plurality of via structures overlying a plurality of second current carrying electrodes of the HEMI semiconductor device, the second plurality of via structures having a second via conductor electrically coupled to the plurality of second current carrying electrodes;

an organic insulator overlying at least a portion of the plurality of first and current carrying electrodes wherein the plurality of first and second via structures extend through the organic insulator;

a first conductor extending to electrically contact the first plurality of via structures wherein the first conductor is substantially planar at least in regions between each via structure of the first plurality of via structures and that is a solderable conductor material that is suitable for plating onto the HEMI semiconductor device;

a second conductor extending to electrically contact the second plurality of via structures wherein the second conductor is substantially planar at least in regions between each via structure of the second plurality of via structures and is a solderable conductor material that is suitable for plating onto the HEMI semiconductor device;

a first connector attached to the first conductor wherein the first connector overlies at least a portion of an active region of the HEMT semiconductor device; and

a second connector attached to the second conductor.

2. The HEMT semiconductor device of claim 1 wherein the first and second connectors are attached to the respective first and second conductors by one of solder or a conductive adhesive.

3. The HEMT semiconductor device of claim 1 wherein the organic insulator is one of polyimide or SOG or PBO.

4. The HEMT semiconductor device of claim 1 wherein the HEMT semiconductor device is devoid of a stiffening layer between the organic insulator and the first or second conductors.

5. The HEMT semiconductor device of claim 1 wherein the first conductor includes a seed conductor layer formed on the organic insulator and a first conductor material plated onto the seed conductor layer.

6. The HEMT semiconductor device of claim 1 wherein a width of a first via structure of the first plurality of via structures increases for increasing distance from a surface of a semiconductor substrate on which the HEMT semiconductor device is formed.

7. The HEMT semiconductor device of claim 1 wherein the plurality of first current carrying electrodes form a drain of a HEMT transistor, the plurality of second current carrying electrodes form a source of the HEMT transistor, and further including a gate conductor underlying the second conductor and positioned between the source and drain wherein the first and second conductors overlie the gate conductor.

8. The HEMT semiconductor device of claim 1 wherein the first and second connectors are formed from one of copper, a copper plated material, silver, or a silver plated material.

9. The HEMT semiconductor device of claim 1 further including a gate pad configured for wire bonding.

10. The HEMT semiconductor device of claim 1 wherein the second connector overlies at least another portion of the active region of the HEMT semiconductor device.

11. The HEMT semiconductor device of claim 1 wherein the first plurality of via structures includes a first opening wherein each first opening extends through an insulator and is formed overlying a corresponding portion of a first current carrying electrode of the plurality of first current carrying electrodes.