IP Library Granted Patent US 9,397,082
Granted Patent B2
US 9,397,082 · App. 14/990,468 · Granted Jul 19, 2016

Multiple die lead frame packaging

Inventors: William E. Edwards (Ann Arbor, MI); Gary C. Johnson (Tempe, AZ)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H01L25/50H01L21/4825H01L21/4842H01L21/565
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Quick Facts
Patent No.
US 9,397,082
App. No.
14/990,468
Granted
Jul 19, 2016
Kind
B2
Abstract

First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame.

Claims (33)

1. A method of packaging a semiconductor device, the method comprising:

mounting first and second semiconductor die to first and second die pads of a lead frame disposed in a lead frame sheet, respectively;

connecting, with a plurality of wire bonds, each post of a plurality of posts of the lead frame to the first and second semiconductor die, each post extending inward from opposite sides of the lead frame between the first and second die pads and being connected with a respective one of a plurality of leads of the lead frame;

encapsulating the first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds in a package; and

shearing the lead frame sheet to define each lead of the plurality of leads;

wherein the plurality of posts comprises first and second sets of posts extending inward from first and second opposite sides of the lead frame, respectively.

2. The method of claim 1 , wherein each post extends laterally across a line that intersects bond pads on the first and second semiconductor die to which the post is connected.

3. The method of claim 1 , wherein the first and second die pads are connected to one another by a connecting bar of the lead frame that extends between the first and second die pads.

4. The method of claim 3 , wherein the connecting bar has a serpentine shape.

5. The method of claim 3 , wherein the connecting bar comprises a central portion oriented in parallel with the plurality of packaging posts.

6. The method of claim 1 , wherein the first and second semiconductor die have layouts that are identical.

7. The method of claim 6 , wherein mounting the first and second semiconductor die comprises orienting the layouts of the first and second semiconductor die 180 degrees relative to one another.

8. The method of claim 1 , wherein mounting the first and second semiconductor die comprises orienting the first and second semiconductor die to position bond pads of the first and second semiconductor die for which the first and second semiconductor die share one of the plurality of leads along a respective inward facing side of the first and second semiconductor die.

9. The method of claim 1 , wherein each packaging post is in contact with a respective one of the plurality of packaging leads.

10. The method of claim 1 , wherein the packaging posts extending from a respective side of the first and second opposite sides are disposed in parallel.

11. The method of claim 1 , wherein encapsulating the first and second semiconductor die comprises performing an overmolding procedure.

12. A method of packaging a semiconductor device, the method comprising:

mounting first and second semiconductor die to first and second die pads of a lead frame disposed in a lead frame sheet, respectively;

connecting, with a plurality of wire bonds, each post of a plurality of posts of the lead frame to the first and second semiconductor die, each post extending inward from opposite sides of the lead frame between the first and second die pads and being connected with a respective one of a plurality of leads of the lead frame;

enclosing the first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds in a package; and

separating the semiconductor device from a remainder of the lead frame sheet to define each lead of the plurality of leads;

wherein the plurality of posts comprises first and second sets of posts extending inward from first and second opposite sides of the lead frame, respectively, and

wherein connecting each post of the plurality of posts comprises:

connecting each post to the first semiconductor die via a first respective wire bond of the plurality of wire bonds; and

connecting each post to the second semiconductor die via a second respective wire bond of the plurality of wire bonds.

13. The method of claim 12 , wherein each post extends laterally across a line that intersects bond pads on the first and second semiconductor die to which the post is connected.

14. The method of claim 12 , wherein the first and second die pads are connected to one another by a connecting bar of the lead frame that extends between the first and second die pads.

15. The method of claim 14 , wherein the connecting bar has a serpentine shape.

16. The method of claim 14 , wherein the connecting bar comprises a central portion oriented in parallel with the plurality of packaging posts.

17. The method of claim 12 , wherein the first and second semiconductor die have layouts that are identical.

18. The method of claim 12 , wherein mounting the first and second semiconductor die comprises orienting the layouts of the first and second semiconductor die 180 degrees relative to one another.

19. The method of claim 12 , wherein mounting the first and second semiconductor die comprises orienting the first and second semiconductor die to position bond pads of the first and second semiconductor die for which the first and second semiconductor die share one of the plurality of leads along a respective inward facing side of the first and second semiconductor die.

20. The method of claim 12 , wherein enclosing the first and second semiconductor die comprises performing an overmolding procedure.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2016
From: EDWARDS, WILLIAM E.; JOHNSON, GARY C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037435/0954 →
Continuity (2)
Division 14189609 · Feb 25, 2014
Related Publication 20160118373A1 · Apr 28, 2016