IP Library Granted Patent US 10,122,259
Granted Patent B2
US 10,122,259 · App. 15/042,357 · Granted Nov 6, 2018

Over power protection for power converter

Inventors: Vaclav Drda (Valasska Bystrice, CZ); Roman Stuler (Karolinka, CZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02M1/32H02M3/3376H02M3/157H02M3/33515H02M7/529H02M2001/0012H02M2001/0058Y02B70/1433Y02B70/1491
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Quick Facts
Patent No.
US 10,122,259
App. No.
15/042,357
Granted
Nov 6, 2018
Kind
B2
Abstract

A power conversion circuit is provided. A power level of the power conversion circuit is determined by taking a first sample of a voltage potential of a resonant capacitor at a first time. A second sample of the voltage potential of the resonant capacitor voltage is taken at a second time. An electric current is determined based on the first sample and second sample.

Claims (43)

1. A power conversion circuit, comprising:

an average current circuit including an input coupled for receiving a sampling signal representative of a current through a primary winding, wherein the average current circuit measures the sampling signal at a first time and a second time;

a power level circuit including a first input coupled to an output of the average current circuit and a second input coupled for receiving an input voltage of the power conversion circuit to determine an input power of the power conversion circuit as a product of the input voltage and a difference between the measurements of the sampling signal at the first time and second time;

a first amplifier including a first input coupled for receiving a power reference and a second input coupled to an output of the power level circuit;

a variable feedback clamp including a control input coupled to an output of the first amplifier; and

a second amplifier including a first input coupled for receiving the sampling signal and a second input coupled to the variable feedback clamp and further coupled for receiving a feedback signal of the power conversion circuit.

2. The power conversion circuit of claim 1 , further including:

a first power transistor including a first conduction terminal coupled for receiving the input voltage, a second conduction terminal coupled to the primary winding, and a control input coupled to an output of the second amplifier; and

a second power transistor including a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a ground terminal, and a control input coupled to the output of the second amplifier.

3. The power conversion circuit of claim 2 , further including a driver logic circuit including an input coupled to the output of the second amplifier, a first output coupled to the control input of the first power transistor, and a second output coupled to the control input of the second power transistor.

4. The power conversion circuit of claim 1 , further including a voltage offset circuit coupled between the sampling signal and the first input of the second amplifier.

5. The power conversion circuit of claim 1 , further including:

a first circuit node adapted for coupling to the primary winding of the power conversion circuit;

a resonant capacitor coupled between the first circuit node and a ground terminal;

a first capacitor coupled between the first circuit node and a second circuit node; and

a second capacitor coupled between the second circuit node and ground terminal, wherein the second circuit node provides the sampling signal.

6. The power conversion circuit of claim 5 , further including a resistor coupled between the second circuit node and the ground terminal.

7. A power conversion circuit, comprising:

an average current circuit including an input coupled for receiving a sampling signal representative of a current through a primary winding, wherein the average current circuit measures the sampling signal at a first time and a second time; and

a power level circuit including a first input coupled to an output of the average current circuit and a second input coupled for receiving an input voltage of the power conversion circuit to determine an input power of the power conversion circuit as a product of the input voltage and a difference between the measurements of the sampling signal at the first time and second time.

8. The power conversion circuit of claim 7 , further including a first amplifier including a first input coupled for receiving a power reference and a second input coupled to an output of the power level circuit.

9. The power conversion circuit of claim 8 , further including:

a variable feedback clamp including a control input coupled to an output of the first amplifier; and

a second amplifier including a first input coupled for receiving the sampling signal and a second input coupled to the variable feedback clamp and further coupled for receiving a feedback signal of the power conversion circuit.

10. The power conversion circuit of claim 9 , further including:

a first power transistor including a first conduction terminal coupled for receiving the input voltage, a second conduction terminal coupled to the primary winding, and a control input coupled to an output of the second amplifier; and

a second power transistor including a first conduction terminal coupled to the second conduction terminal of the first transistor, a second conduction terminal coupled to a ground terminal, and a control input coupled to the output of the second amplifier.

11. The power conversion circuit of claim 10 , further including a driver logic circuit including an input coupled to the output of the second amplifier, a first output coupled to the control input of the first power transistor, and a second output coupled to the control input of the second power transistor.

12. The power conversion circuit of claim 9 , further including a voltage offset circuit coupled between the sampling signal and the first input of the second amplifier.

13. The power conversion circuit of claim 7 , further including:

a first circuit node adapted for coupling to the primary winding of the power conversion circuit;

a resonant capacitor coupled between the first circuit node and a ground terminal;

a first capacitor coupled between the first circuit node and a second circuit node; and

a second capacitor coupled between the second circuit node and ground terminal, wherein the second circuit node provides the sampling signal.

14. A method of determining an input power for a power conversion circuit, comprising:

measuring a sampling signal representative of a current through a primary winding at a first time and a second time; and

determining the input power as a product of an input voltage of the power conversion circuit and a difference between the measurements of the sampling signal at the first time and second time.

15. The method of claim 14 , further including comparing the determined input power and a power reference.

16. The method of claim 15 , further including clamping a feedback signal of the power conversion circuit in response to comparing the determined input power and the power reference.

17. The power conversion circuit of claim 16 , further including comparing the sampling signal to the clamped feedback signal.

18. The power conversion circuit of claim 17 , further including controlling a power transistor in response to comparing the sampling signal to the clamped feedback signal.

19. The method of claim 14 , further including sensing the current through the primary winding as a voltage across a resonant capacitor.

20. The method of claim 19 , further including dividing down the voltage across the resonant capacitor as the sampling signal.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2016
From: DRDA, VACLAV; STULER, ROMAN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 037723/0334 →
Continuity (2)
Provisional Application 62219531 · Sep 16, 2015
Related Publication 20170077798A1 · Mar 16, 2017