IP Library Granted Patent US 10,488,516
Granted Patent B2
US 10,488,516 · App. 15/092,982 · Granted Nov 26, 2019

Controlling an output signal independently of the first harmonic

Inventors: Johan Camiel Julia Janssens (Asse, BE); Pavel Horsky (Brno, CZ); Petr Kamenicky (Brno, CZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G01S15/931G01S2015/932
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,488,516
App. No.
15/092,982
Granted
Nov 26, 2019
Kind
B2
Abstract

A method includes configuring a transmitter to provide at least three output levels used to form an output signal. The method further includes adjusting a duration of at least one of the output levels to control an average value of the output signal independently of an amplitude of a first harmonic of the output signal.

Claims (42)

1. An integrated circuit comprising:

a transmitter that cyclically forms an output signal using at least three voltage states, the output signal having:

an average value V DCB ;

an amplitude V F of a fundamental frequency component; and

a period T of the fundamental frequency component, the period T including:

a duration D 0 of an intermediate state voltage;

a duration D + of a high state voltage above the intermediate state voltage; and

a duration D − of a low state voltage below the intermediate state voltage; and

processing logic that controls the average value V DCB by adjusting at least one of duration D + and duration D − to vary a difference therebetween.

2. The integrated circuit of claim 1 , further comprising a receiver with an input terminal configured to directly connect with a piezoelectric transducer driven by the output signal, the average value V DCB corresponding to a desired DC bias for the input terminal.

3. The integrated circuit of claim 1 , wherein the processing logic further controls the amplitude V F by adjusting at least one of duration D + and duration D − to vary their sum.

4. The integrated circuit of claim 3 , wherein the processing logic controls the amplitude V F by varying both duration D + and duration D − to maintain the difference therebetween.

5. The integrated circuit of claim 3 , wherein the processing logic controls the amplitude V F by measuring a supply voltage and responsively adjusting at least one of duration D + and duration D − .

6. The integrated circuit of claim 5 , wherein the intermediate state voltage is a ground voltage, the high state voltage is a positive voltage, and the low state voltage is a negative voltage, and wherein the integrated circuit comprises a charge pump that provides both the positive and negative voltages.

7. A method that comprises manufacturing an integrated circuit having:

a transmitter that cyclically forms an output signal using at least three voltage states, the output signal having:

an average value V DCB ;

an amplitude V F of a fundamental frequency component; and

a period T of the fundamental frequency component, the period T including:

a duration D 0 of an intermediate state voltage;

a duration D + of a high state voltage above the intermediate state voltage; and

a duration D − of a low state voltage below the intermediate state voltage; and

processing logic that controls the average value V DCB by adjusting at least one of duration D + and duration D − to vary a difference therebetween.

8. The method of claim 7 , wherein the integrated circuit further includes a receiver with an input terminal configured to directly connect with a piezoelectric transducer driven by the output signal, the average value V DCB corresponding to a desired DC bias for the input terminal.

9. The method of claim 7 , wherein the processing logic further controls the amplitude V F by adjusting at least one of duration D + and duration D − to vary their sum.

10. The method of claim 9 , wherein the processing logic controls the amplitude V F by varying both duration D + and duration D − to maintain the difference therebetween.

11. The method of claim 9 , wherein the processing logic controls the amplitude V F by measuring a supply voltage and responsively adjusting at least one of duration D + and duration D − .

12. The method of claim 11 , wherein the intermediate state voltage is a ground voltage, the high state voltage is a positive voltage, and the low state voltage is a negative voltage, and wherein the integrated circuit comprises a charge pump that provides both the positive and negative voltages.

13. A method comprising:

cyclically forming an output signal using at least three voltage states, the output signal having:

an average value V DCB ;

an amplitude V F of a fundamental frequency component; and

a period T of the fundamental frequency component, the period T including:

a duration Do of an intermediate state voltage;

a duration D + of a high state voltage above the intermediate state voltage; and

a duration D − of a low state voltage below the intermediate state voltage; and

controlling the average value V DCB by adjusting at least one of duration D + and duration D − to vary a difference therebetween.

14. The method of claim 13 , further comprising applying the output signal to a piezoelectric transducer terminal, the terminal being electrically connected to a receiver input without a coupling capacitor.

15. The method of claim 13 , further comprising:

controlling the amplitude V F by adjusting at least one of duration D + and duration D − to vary their sum.

16. The method of claim 15 , wherein controlling the amplitude V F is performed by varying both duration D + and duration D − to maintain the difference therebetween.

17. The method of claim 15 , wherein controlling the amplitude V F includes measuring a supply voltage and responsively adjusting at least one of duration D + and duration D − .

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2016
From: JANSSENS, JOHAN CAMIEL JULIA; HORSKY, PAVEL; KAMENICKY, PETR
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038219/0203 →
Continuity (2)
Provisional Application 62244549 · Oct 21, 2015
Related Publication 20170115391A1 · Apr 27, 2017