IP Library Granted Patent US 9,799,559
Granted Patent B1
US 9,799,559 · App. 15/158,827 · Granted Oct 24, 2017

Methods employing sacrificial barrier layer for protection of vias during trench formation

Inventors: Shariq Siddiqui (Albany, NY); Frank W. Mont (Troy, NY); Xunyuan Zhang (Albany, NY); Brown Peethala (Albany, NY); Douglas M. Trickett (Altamont, NY)
Assignees: GLOBALFOUNDRIES Inc.; International Business Machines Corporation
H01L21/7688H01L21/76843H01L21/76865H01L21/76883H01L23/528H01L23/5226H01L23/53219H01L23/53223H01L23/53228H01L23/53257
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Quick Facts
Patent No.
US 9,799,559
App. No.
15/158,827
Granted
Oct 24, 2017
Kind
B1
Abstract

A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.

Claims (28)

1. A method comprising:

providing an intermediate semiconductor structure comprising an interconnecting conductive structure, a dielectric layer and a patternable layer disposed over the interconnecting conductive structure, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask, the patternable layer, the dielectric layer, and opening directly onto the interconnecting conductive structure;

depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias and directly on the interconnecting conductive structure;

first removing an upper portion of the sacrificial barrier layer between the plurality of vias while maintaining a lower portion of the sacrificial barrier layer directly on the interconnecting conductive structure in the plurality of vias;

forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias while maintaining the lower portion of the sacrificial barrier layer directly on the interconnecting conductive structure in the plurality of vias; and

second removing the remaining lower portions of the sacrificial barrier layer from the plurality of vias to expose the interconnecting conductive structure at the bottom of the vias.

2. The method of claim 1 wherein the sacrificial barrier layer is non-reactive with patternable layer forming sides of the plurality of vias.

3. The method of claim 1 wherein the sacrificial barrier layer is non-reactive with the interconnecting conductive structure.

4. The method of claim 1 wherein the sacrificial barrier layer is non-reactive with the forming the trench in the patternable layer.

5. The method of claim 1 wherein a spacing between one of the plurality of vias and the trench is less than about 20 nanometers.

6. The method of claim 1 wherein the sacrificial barrier layer comprises an atomic layer deposition (ALD).

7. The method of claim 1 wherein the sacrificial barrier layer comprises AlN or TiN.

8. The method of claim 7 wherein the removing portions of the sacrificial barrier layer comprises removing portions of the sacrificial barrier layer corresponding to the trench patterning memorization.

9. The method of claim 1 wherein the multilayer stack structure comprises a trench patterning memorization corresponding to the trench.

10. The method of claim 1 wherein the forming the trenches comprises etching.

11. The method of claim 1 further comprising filling the plurality of vias in the patternable layer with a conductive material.

12. The method of claim 1 further comprising filling the trench in the patternable layer with a conductive or non-conductive material.

13. The method of claim 1 wherein:

the depositing comprises depositing a fill material over the sacrificial barrier layer and in a plurality of cavities defined by the sacrificial barrier layer in the plurality of vias;

the first removing comprises removing a portion of the fill material and the portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer and a portion of the fill material in the plurality of vias; and

the second removing comprises removing the remaining fill material and the remaining portions of the sacrificial barrier layer from the plurality of vias.

14. The method of claim 13 wherein the sacrificial barrier layer is non-reactive with patternable layer forming sides of the plurality of vias.

15. The method of claim 13 wherein the sacrificial barrier layer is non-reactive with the interconnecting conductive structure.

16. The method of claim 13 wherein the sacrificial barrier layer is non-reactive with the forming the trench in the patternable layer.

17. The method of claim 13 wherein the sacrificial barrier layer comprises an atomic layer deposition (ALD).

18. The method of claim 17 wherein the sacrificial barrier layer comprises AlN or TiN.

19. The method of claim 13 wherein a distance from the via to the trench is less than about 20 nanometers.

20. The method of claim 13 further comprising filling in the plurality of vias with a conductive material and filling the trenches with a dielectric or a conductive material.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2016
From: SIDDIQUI, SHARIQ; MONT, FRANK W.; ZHANG, XUNYUAN
To: GLOBALFOUNDRIES INC.
Reel/Frame 038646/0654 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2016
From: PEETHALA, BROWN; TRICKETT, DOUGLAS M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038756/0383 →