Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure

1. A monolithic three-dimensional memory device comprising:

a lower tier structure comprising a first alternating stack of first insulating layers and first electrically conductive layers and located over a substrate;

an upper tier structure comprising a second alternating stack of second insulating layers and second electrically conductive layers and located over the lower tier structure;

memory stack structures and support pillar structures extending through the second alternating stack and at least an upper portion of the first alternating stack; and

support pillar structures extending through the second alternating stack,

wherein:

each of the memory stack structures and support pillar structures comprises a respective vertical semiconductor material layer; and

each vertical semiconductor material layer in the support pillar structures has a bottommost surface located above a horizontal plane including bottommost surfaces of vertical semiconductor material layers within the memory stack structures.

2. The monolithic three-dimensional memory device of claim 1 , further comprising doped semiconductor material portions and intrinsic semiconductor material portions,

wherein:

each of the support pillar structures overlies one of the doped semiconductor material portions in contact with a bottom surface of a respective vertical semiconductor material layer; and

each of the doped semiconductor material portions overlies a respective one of the intrinsic semiconductor material portions.

3. The monolithic three-dimensional memory device of claim 2 , further comprising an etch stop layer which comprises:

a first horizontal portion located between the first alternating stack and the second alternating stack;

a second horizontal portion located between the intrinsic semiconductor material portions and the substrate; and

vertical portions laterally surrounding respective doped semiconductor material portions.

4. The monolithic three-dimensional memory device of claim 3 , further comprising:

first epitaxial semiconductor portions underlying respective memory stack structures; and

second epitaxial semiconductor portions underlying the support pillar structures.

5. The monolithic three-dimensional memory device of claim 4 , wherein:

the second horizontal portion of the etch stop layer is located between the intrinsic semiconductor material portions and the second epitaxial semiconductor portions; and

each of the first and second epitaxial semiconductor portions includes a respective single crystalline semiconductor material that is epitaxially aligned to a single crystalline semiconductor material of the substrate.

6. The monolithic three-dimensional memory device of claim 5 , wherein:

the semiconductor material portions comprise polysilicon or amorphous silicon;

the intrinsic semiconductor material portions comprise undoped polysilicon or undoped amorphous silicon; and

the doped semiconductor material portions comprise boron-doped polysilicon or boron-doped amorphous silicon.

7. The monolithic three-dimensional memory device of claim 1 , wherein a first horizontal plane including bottommost surfaces of vertical semiconductor material layers in the memory stack structures is vertically spaced from a second horizontal plane including bottommost surfaces of vertical semiconductor material layers in the support pillar structures by a vertical distance greater than 50% of a total thickness of the first alternating stack.

8. The monolithic three-dimensional memory device of claim 1 , further comprising a staircase region in which each electrically conductive layer laterally extends farther than any overlying electrically conductive layer.

9. The monolithic three-dimensional memory device of claim 8 , wherein:

the support pillar structures are located in the staircase region; and

the memory stack structures extend through a memory array region.

10. The monolithic three-dimensional memory device of claim 1 , wherein each of the memory stack structures and support pillar structures comprises a lateral stack of a memory film comprising a charge trapping material and a tunneling dielectric that laterally surrounds a respective vertical semiconductor material layer.

11. The monolithic three-dimensional memory device of claim 1 , further comprising:

drain regions contacting a top portion of each vertical semiconductor material layer in the memory stack structures;

dummy drain regions contacting a top portion of each vertical semiconductor material layer in the support pillar structures;

a contact level dielectric layer contacting an entirety of all top surfaces of the dummy drain regions; and

drain contact via structures extending through the contact level dielectric layer and contacting the drain regions.

12. The three-dimensional memory device of claim 1 , wherein:

the three-dimensional memory device comprises a vertical NAND device located over the substrate;

the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises:

a plurality of semiconductor channels including the vertical semiconductor layers within the memory stack structures;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.