SYSTEM AND METHOD FOR CHARACTERIZING CRITICAL PARAMETERS RESULTING FROM A SEMICONDUCTOR DEVICE FABRICATION PROCESS

1 . A process control monitoring system formed on a substrate comprising:

a first structure formed in a structural layer of said substrate, said first structure including a first finger interposed between a first pair of sidewalls, said first finger exhibiting a first length and a first width, each of which is parallel to a surface of said substrate, and said first finger being separated from each of said first pair of sidewalls by a first gap having a first spacing;

a second structure formed in said structural layer of said substrate, said second structure including a second finger interposed between a second pair of sidewalls, said second finger exhibiting a second length and said first width, each of which is parallel to said surface of said substrate, and said second finger being separated from each of said second pair of sidewalls by a second gap having said first spacing; and

a third structure formed in said structural layer of said substrate, said third structure including a third finger interposed between a third pair of sidewalls, said third finger exhibiting said second length and a second width, each of which is parallel to said surface of said substrate, and said third finger being separated from each of said third pair of sidewalls by a third gap having a second spacing.

2 . The process control monitoring system of claim 1 wherein:

said first length differs from said second length;

said first width differs from said second width; and

said first spacing differs from said second spacing.

3 . The process control monitoring system of claim 2 wherein:

said first width is equivalent to said first spacing; and

said second width is equivalent to said second spacing.

4 . The process control monitoring system of claim 1 wherein each of said first, second, and third fingers exhibits a thickness perpendicular to said surface of said substrate, said thickness being equivalent for said each of said first, second, and third fingers.

5 . The process control monitoring system of claim 1 wherein said first, second, and third fingers are immovable relative to corresponding said first, second, and third pairs of sidewalls.

6 . The process control monitoring system of claim 1 wherein:

each of said first, second, and third fingers includes a first end and a second end; and

for said each of said first, second, and third fingers, said process control monitoring system further comprises a first pair of terminals in electrical communication with said first end and a second pair of terminals in electrical communication with said second end, said first and second pair of terminals being configured for connection with a four terminal resistance measurement device to determine a resistance of said each of said first, second, and third fingers.

7 . The process control monitoring system of claim 6 wherein:

each of said first, second, and third pairs of sidewalls includes a first sidewall and a second sidewall; and

for said each of said first, second, and third pairs of sidewalls, said process control monitoring system further comprises a first contact and a second contact, said first contact being in electrical communication with said first sidewall, and said second contact being in electrical communication with said second sidewall, wherein said first and second electrical contacts are configured for connection with a capacitance measurement device at a first potential and said first and second pairs of terminals are further configured for connection with said capacitance measurement device at a second potential for determining a capacitance between said each of said first, second, and third fingers and associated said each of said first, second, and third pairs of sidewalls.

8 . The process control monitoring system of claim 1 wherein said first and second lengths, said first and second widths, and said first and second spacings for associated ones of said first, second, and third fingers are utilized to determine an etch undercut parameter of said first, second, and third fingers.

9 . The process control monitoring system of claim 1 wherein said first and second lengths, said first and second widths, and said first and second spacings for associated ones of said first, second, and third fingers are utilized to determine a resistivity parameter of said substrate.

10 . The process control monitoring system of claim 1 wherein said first and second lengths, said first and second widths, and said first and second spacings for associated ones of said first, second, and third fingers are utilized to determine a thickness parameter of said structural layer perpendicular to said surface of said substrate.

11 . A wafer structure including the process control monitoring system of claim 1 , wherein said wafer structure further comprises a plurality of semiconductor devices formed in said structural layer, said process control monitoring system and said plurality of semiconductor devices being fabricated concurrently using the same semiconductor device fabrication process.

12 . A method of characterizing critical parameters resulting from a semiconductor device fabrication process comprising:

implementing said semiconductor device fabrication process to form a process control monitoring system in a structural layer of a substrate, said process control monitoring system including:

a first structure including a first finger interposed between a first pair of sidewalls, said first finger exhibiting a first length and a first width, each of which is parallel to a surface of said substrate, and said first finger being separated from each of said first pair of sidewalls by a first gap having a first spacing;

a second structure including a second finger interposed between a second pair of sidewalls, said second finger exhibiting a second length and said first width, each of which is parallel to said surface of said substrate, and said second finger being separated from each of said second pair of sidewalls by a second gap having said first spacing; and

a third structure including a third finger interposed between a third pair of sidewalls, said third finger exhibiting said second length and a second width, each of which is parallel to said surface of said substrate, and said third finger being separated from each of said third pair of sidewalls by a third gap having a second spacing; and

determining said critical parameters based on said first and second lengths, said first and second widths, and said first and second spacings for associated ones of said first, second, and third fingers.

13 . The method of claim 12 wherein said implementing operation forms said process control monitoring system to have said first, second, third fingers that are immovable relative to corresponding said first, second, and third pairs of sidewalls.

14 . The method of claim 12 wherein said determining comprises:

determining a first resistance of said first finger;

determining a first capacitance between said first pair of sidewalls and said first finger;

determining a second resistance of said second finger;

determining a second capacitance between said second pair of sidewalls and second first finger;

determining a third resistance of said third finger;

determining a third capacitance between said third pair of sidewalls and third first finger; and

computing said critical parameters based on said first, second, and third resistances and said first, second, and third capacitances.

15 . The method of claim 14 wherein said determining each of said first, second, and third resistances comprises measuring a Kelvin resistance of said each of said first, second, and third fingers.

16 . The method of claim 14 wherein said computing operation comprises:

computing an etch undercut parameter;

computing a resistivity parameter of said substrate; and

computing a thickness parameter of said structural layer perpendicular to said surface of said substrate, said etch undercut parameter, said resistivity parameter, and said thickness parameter being said critical parameters, and each of said etch undercut parameter, said resistivity parameter, and said thickness parameter being computed utilizing said first, second, and third resistances and said first, second, and third capacitances.

17 . The method of claim 12 further comprising implementing said semiconductor device fabrication process to produce a wafer structure that includes said process control monitoring system and a plurality of semiconductor devices in said structural layer, wherein said critical parameters determined utilizing said first, second, and third structures of said process control monitoring system characterizes said critical parameters of said plurality of said semiconductor devices.

18 . A wafer structure comprising:

a substrate;

a plurality of semiconductor devices formed in a structural layer of said substrate; and

a process control monitoring system formed in a structural layer of said substrate, wherein said plurality of semiconductor devices and said process control monitoring system are fabricated concurrently using the same semiconductor device fabrication process, said process control monitoring system including:

a first structure including a first finger interposed between a first pair of sidewalls, said first finger exhibiting a first length and a first width, each of which is parallel to a surface of said substrate, and said first finger being separated from each of said first pair of sidewalls by a first gap having a first spacing;

a second structure including a second finger interposed between a second pair of sidewalls, said second finger exhibiting a second length and said first width, each of which is parallel to said surface of said substrate, and said second finger being separated from each of said second pair of sidewalls by a second gap having said first spacing; and

a third structure including a third finger interposed between a third pair of sidewalls, said third finger exhibiting said second length and a second width, each of which is parallel to said surface of said substrate, and said third finger being separated from each of said third pair of sidewalls by a third gap having a second spacing, wherein said first and second lengths, said first and second widths, and said first and second spacings for associated ones of said first, second, and third fingers are utilized to determine critical parameters of said plurality of said semiconductor devices resulting from said semiconductor device fabrication process.

19 . The wafer structure of claim 18 wherein:

said first length differs from said second length;

said first width differs from said second width; and

said first spacing differs from said second spacing.

20 . The wafer structure of claim 18 wherein said first, second, and third fingers are immovable relative to corresponding ones of said first, second, and third pairs of sidewalls.