Integration Of Metal Floating Gate In Non-Volatile Memory
A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.
1 . A non-volatile memory cell, comprising:
a silicon substrate;
source and drain regions formed in the silicon substrate, wherein a channel region of the substrate is defined between the source and drain regions;
a metal floating gate disposed over and insulated from a first portion of the channel region;
a metal control gate disposed over and insulated from the metal floating gate;
a polysilicon erase gate disposed over and insulated from the source region; and
a polysilicon word line gate disposed over and insulated from a second portion of the channel region.
2 . The non-volatile memory cell of claim 1 , wherein the metal floating gate is insulated from the substrate by a layer of high K dielectric material.
3 . The non-volatile memory cell of claim 2 , wherein the high K dielectric material is at least one of HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , and nitridation treated oxide.
4 . The non-volatile memory cell of claim 2 , wherein the metal floating gate is further insulated from the substrate by a layer of oxide.
5 . The non-volatile memory cell of claim 4 , wherein the metal floating gate comprises TiN.
6 . The non-volatile memory cell of claim 1 , wherein the metal floating gate comprises at least one of TaN, TaSiN, TiN/TiAl/TiN, and TiN/AlN/TiN.
7 . The non-volatile memory cell of claim 1 , wherein the metal floating gate comprises Al and at least one of TiN and TaN.
8 . The non-volatile memory cell of claim 1 , wherein the metal floating gate comprises AlN and TiN.
9 . The non-volatile memory cell of claim 1 , wherein the metal control gate is insulated from the metal floating gate by one or more high K dielectric materials.
10 . The non-volatile memory cell of claim 1 , wherein the metal control gate is insulated from the metal floating gate by a layer of Al 2 O 3 disposed between layers of HfO 2 .
11 . The non-volatile memory cell of claim 1 , wherein the metal control gate comprises at least one of TaN, TaSiN, TiN/TiAl/TiN, TiN/AlN/TiN and W.
12 . A method of forming a non-volatile memory cell, comprising:
forming source and drain regions in a silicon substrate, wherein a channel region of the substrate is defined between the source and drain regions;
forming a first insulation layer on the substrate;
forming a metal floating gate on the first insulation layer and over a first portion of the channel region;
forming a second insulation layer on the metal floating gate;
forming a metal control gate on the second insulation layer and over the metal floating gate;
forming a polysilicon erase gate over and insulated from the source region; and
forming a polysilicon word line gate over and insulated from a second portion of the channel region.
13 . The method of claim 12 , wherein the first insulation layer comprises a high K dielectric material.
14 . The method of claim 13 , wherein the high K dielectric material is at least one of HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , and nitridation treated oxide.
15 . The method of claim 12 , wherein the first insulation layer comprises an oxide layer and a layer of high K dielectric material.
16 . The method of claim 15 , wherein the metal floating gate comprises TiN.
17 . The method of claim 12 , wherein the metal floating gate comprises at least one of TaN, TaSiN, TiN/TiAl/TiN, and TiN/AlN/TiN.
18 . The method of claim 12 , wherein the metal floating gate comprises Al and at least one of TiN and TaN.
19 . The method of claim 12 , wherein the metal floating gate comprises AlN and TiN.
20 . The method of claim 12 , wherein the forming of the second insulation layer comprises:
depositing insulation material on the metal floating gate; and
annealing the deposited insulation material.
21 . The method of claim 12 , wherein the second insulation layer comprises one or more high K dielectric materials.
22 . The method of claim 12 , wherein the second insulation layer comprises a layer of Al 2 O 3 disposed between layers of HfO 2 .
23 . The method of claim 12 , wherein the metal control gate comprises at least one of TaN, TaSiN, TiN/TiAl/TiN, TiN/AlN/TiN and W.