IP Library Granted Patent US 10,511,305
Granted Patent B2
US 10,511,305 · App. 15/388,774 · Granted Dec 17, 2019

Capacitive sensing

Inventor: John Stanley Dubery (Basingstoke, GB)
Assignee: Neodrón Limited
H03K17/962G01D1/00G01D5/24G01D15/00G01D21/00G01R29/0878H03K17/9622H03K2217/960725
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Quick Facts
Patent No.
US 10,511,305
App. No.
15/388,774
Granted
Dec 17, 2019
Kind
B2
Abstract

In one embodiment, a device includes a multi-channel capacitive sensor and a control circuit. The control circuit is configured to ground a first sense capacitor and a second sense capacitor of the multi-channel capacitive sensor. The first sense capacitor and the second sense capacitor are adapted to be connected to a drive line. The control circuit is configured to charge, by a first voltage provided on a pin of the controller, an in-series combination of a sample capacitor and the first sense capacitor while not charging the second sense capacitor by the first voltage provided on the pin of the controller. The control circuit is further configured to measure a second voltage on the pin of the controller resulting at least in part from charging the in-series combination, the second voltage providing an indication of a capacitance of the first sense capacitor.

Claims (40)

1. A device comprising:

a multi-channel capacitive sensor comprising a drive line; and

a control circuit configured to:

ground a first sense capacitor and a second sense capacitor of the multichannel capacitive sensor, wherein the first sense capacitor and the second sense capacitor are adapted to be connected to the drive line;

charge, by a first voltage provided on a pin of the control circuit, an in-series combination of a sample capacitor and the first sense capacitor using forward conduction of a drive signal by a first diode coupled to the first sense capacitor;

preventing charging of the second sense capacitor, during said charge of the in-series combination of the sample capacitor and the first sense capacitor, by reverse biasing a second diode coupling the second sense capacitor to the pin of the control circuit having the first voltage; and

measure a second voltage on the pin of the control circuit resulting at least in part from charging the in-series combination of the sample capacitor and the first sense capacitor, wherein the second voltage provides an indication of a capacitance of the first sense capacitor.

2. The device of claim 1 , wherein the control circuit is further configured to:

ground the first sense capacitor and the second sense capacitor after charging the in-series combination of the sample capacitor and the first sense capacitor;

charge, by a third voltage provided on the pin of the control circuit, an in-series combination of the sample capacitor and the second sense capacitor while not charging the first sense capacitor by the third voltage provided on the pin of the control circuit; and

measure a fourth voltage on the pin of the control circuit resulting at least in part from charging the in-series combination of the sample capacitor and the second sense capacitor, wherein the fourth voltage provides an indication of a capacitance of the second sense capacitor.

3. The device of claim 1 , wherein the control circuit is further configured to repeat the charging and measuring operations until the measured second voltage exceeds a measurement threshold.

4. The device of claim 1 , wherein the control circuit is further configured to provide a bias signal, by a second pin of the control circuit, to prevent a second diode coupled to the second sense capacitor from forward conducting a drive signal to the second sense capacitor.

5. The device of claim 1 , wherein the control circuit is further configured to compare the capacitance of the first sense electrode with a capacitance of a second sense electrode.

6. The device of claim 1 , wherein the control circuit is further configured to provide a time gap between charging the in-series combination and measuring the second voltage.

7. The device of claim 1 , wherein the control circuit is further configured to ground the first sense capacitor while measuring the second voltage.

8. A non-transitory computer-readable medium comprising logic, the logic when executed by one or more processors configured to cause the one or more processors to perform operations comprising:

grounding a first sense capacitor and a second sense capacitor of a multi-channel capacitive sensor, wherein the first sense capacitor and the second sense capacitor are adapted to be connected to a drive line;

charging, by a first voltage provided on a pin of a controller, an in-series combination of a sample capacitor and the first sense capacitor using forward conduction of a drive signal by a first diode coupled to the first sense capacitor;

preventing charging of the second sense capacitor, during said charge of the in-series combination of the sample capacitor and the first sense capacitor, by reverse biasing a second diode coupling the second sense capacitor to the pin of the control circuit having the first voltage; and

measuring a second voltage on the pin of the controller resulting at least in part from charging the in-series combination of the sample capacitor and the first sense capacitor, wherein the second voltage provides an indication of a capacitance of the first sense capacitor.

9. The non-transitory computer-readable medium of claim 8 , wherein the operations further comprise:

grounding the first sense capacitor and the second sense capacitor after charging the in-series combination of the sample capacitor and the first sense capacitor;

charging, by a third voltage provided on the pin of the controller, an in-series combination of the sample capacitor and the second sense capacitor while not charging the first sense capacitor by the third voltage provided on the pin of the controller; and

measuring a fourth voltage on the pin of the controller resulting at least in part from charging the in-series combination of the sample capacitor and the second sense capacitor, wherein the fourth voltage provides an indication of a capacitance of the second sense capacitor.

10. The non-transitory computer-readable medium of claim 8 , wherein the operations further comprise repeating the charging and measuring operations until the measured second voltage exceeds a measurement threshold.

11. The non-transitory computer-readable medium of claim 8 , wherein the operations further comprise providing a bias signal, by a second pin of the controller, to prevent a second diode coupled to the second sense capacitor from forward conducting a drive signal to the second sense capacitor.

12. The non-transitory computer-readable medium of claim 8 , wherein the operations further comprise comparing the capacitance of the first sense electrode with a capacitance of a second sense electrode.

13. The non-transitory computer-readable medium of claim 8 , wherein the operations further comprise providing a time gap between charging the in-series combination and measuring the second voltage.

14. The non-transitory computer-readable medium of claim 8 , wherein the operations further comprise grounding the first sense capacitor while measuring the second voltage.

15. A method, comprising:

grounding a first sense capacitor and a second sense capacitor of a multi-channel capacitive sensor, wherein the first sense capacitor and the second sense capacitor are adapted to be connected to a drive line;

charging, by a first voltage provided on a pin of a controller, an in-series combination of a sample capacitor and the first sense capacitor using forward conduction of a drive signal by a first diode coupled to the first sense capacitor;

preventing charging of the second sense capacitor, during said charge of the in-series combination of the sample capacitor and the first sense capacitor, by reverse biasing a second diode coupling the second sense capacitor to the pin of the control circuit having the first voltage; and

measuring a second voltage on the pin of the controller resulting at least in part from charging the in-series combination of the sample capacitor and the first sense capacitor, wherein the second voltage provides an indication of a capacitance of the first sense capacitor.

16. The method of claim 15 , further comprising:

grounding the first sense capacitor and the second sense capacitor after charging the in-series combination of the sample capacitor and the first sense capacitor;

charging, by a third voltage provided on the pin of the controller, an in-series combination of the sample capacitor and the second sense capacitor while not charging the first sense capacitor by the third voltage provided on the pin of the controller; and

measuring a fourth voltage on the pin of the controller resulting at least in part from charging the in-series combination of the sample capacitor and the second sense capacitor, wherein the fourth voltage provides an indication of a capacitance of the second sense capacitor.

17. The method of claim 15 , further comprising repeating the charging and measuring operations until the measured second voltage exceeds a measurement threshold.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2019
From: MICROCHIP TECHNOLOGY INC.; ATMEL CORPORATION; MICROCHIP TECHNOLOGY GERMANY GMBH
To: NEODRÓN LIMITED
Reel/Frame 048259/0840 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENT RIGHTS Recorded Dec 21, 2018
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 047976/0884 →
RELEASE OF SECURITY INTEREST IN CERTAIN PATENT RIGHTS Recorded Dec 21, 2018
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; ATMEL CORPORATION
Reel/Frame 047976/0937 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: DUBERY, JOHN STANLEY
To: ATMEL CORPORATION
Reel/Frame 041729/0784 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
Continuity (3)
Continuation 13537986 · Jun 29, 2012
Continuation 12395880 · Mar 2, 2009
Related Publication 20170170825A1 · Jun 15, 2017