Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.
1. A semiconductor device comprising:
a data terminal;
a calibration terminal;
a first power supply line configured to be supplied with a first power supply potential;
a second power supply line configured to be supplied with a second power supply potential;
a first transistor unit coupled between the first power supply line and the data terminal;
a plurality of second transistor units coupled between the second power supply line and the calibration terminal, wherein each second transistor unit of the plurality of second transistor units comprises a plurality of transistors coupled to a resistor, the plurality of transistors and the resistor are not shared with other second transistor units, and the plurality of second transistor units are connected in parallel to each other so that an impedance of each of the second transistor units is adjustable using an impedance code; and
an impedance control circuit configured to adjust the impedance of each of the second transistor units so that a potential of the calibration terminal matches a reference potential, the impedance control circuit reflecting the impedance of one of the second transistor units to the first transistor unit; and
wherein the reference potential is different in potential level from an intermediate potential between the first power supply potential and the second power supply potential.
2. The semiconductor device of claim 1 , wherein the first power supply potential is VDDQ and wherein the reference potential is 0.8 VDDQ.
3. The semiconductor device of claim 1 , wherein the first power supply potential is VDDQ and wherein the reference potential is greater than 0.5 VDDQ and less than VDDQ.
4. A system comprising:
a first semiconductor device comprising:
a first data input/output (I/O) terminal; and
a first calibration terminal; and
a controller comprising:
a control circuit;
a data I/O circuit;
a second data I/O terminal, the second data I/O terminal being coupled to the data I/O circuit and the second data I/O terminal being coupled to the first data I/O terminal of the first semiconductor device;
a calibration terminal;
a first transistor unit coupled to the second data I/O terminal, the first transistor unit including a plurality of first transistors having a first conductivity type connected in parallel to each other, wherein an impedance of the first transistor unit is adjustable;
a plurality of second transistor units coupled to the calibration terminal, each of the second transistor units including a plurality of second transistors having the first conductivity type connected in parallel to each other, the plurality of second transistors coupled to a resistor, and the plurality of second transistors and the resistor are not shared with other second transistor units, wherein an impedance of each of the second transistor units is adjustable; and
an impedance control circuit configured to:
adjust the impedance of each of the second transistor units so that a potential of the calibration terminal matches a reference potential; and
control an impedance of the first transistor unit in accordance with the adjusted impedance of the second transistor units.
5. The system of claim 4 , wherein the first power supply potential is VDDQ and wherein the reference potential is 0.8 VDDQ.
6. The system of claim 4 , wherein the first power supply potential is VDDQ and wherein the reference potential is greater than 0.5 VDDQ and less than VDDQ.
7. A controller for operating a semiconductor device, the controller comprising:
a control circuit;
a data input/output (I/O) circuit; and
a data I/O terminal coupled to the data I/O circuit, wherein the data I/O terminal is configured to be coupled to a data I/O terminal of a semiconductor device;
a calibration terminal;
a first transistor unit coupled to the data I/O terminal, the first transistor unit including a plurality of first transistors having a first conductivity type connected in parallel to each other, wherein an impedance of the first transistor unit is adjustable;
a plurality of second transistor units coupled to the calibration terminal, each of the second transistor units including a plurality of second transistors having the first conductivity type connected in parallel to each other, the plurality of second transistors coupled to a resistor, and the plurality of second transistors and the resistor are not shared with other second transistor units, wherein an impedance of each of the second transistor units is adjustable; and
an impedance control circuit configured to:
adjust the impedance of each of the second transistor units so that a potential of the calibration terminal matches a reference potential; and
control an impedance of the first transistor unit in accordance with the adjusted impedance of the second transistor units.
8. The controller of claim 7 , wherein the first power supply potential is VDDQ and wherein the reference potential is 0.8 VDDQ.
9. The controller of claim 7 , wherein the first power supply potential is VDDQ and wherein the reference potential is greater than 0.5 VDDQ and less than VDDQ.