Multi-step voltage for forming resistive access memory (RRAM) cell filament
A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
1. A method of forming a conductive filament in metal oxide material disposed between and in electrical contact with first and second conductive electrodes, the method comprising:
applying a plurality of voltage pulses spaced apart in time across the first and second electrodes;
wherein for each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
2. The method of claim 1 , wherein for each of the voltage pulses, a maximum of the voltage amplitude exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
3. The method of claim 1 , wherein for each of the voltage pulses, further comprising:
limiting electrical current applied across the first and second electrodes during the voltage pulse to a current limit.
4. The method of claim 3 , wherein for each one of the voltage pulses, the current limit exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
5. The method of claim 4 , wherein for each one of the voltage pulses, the current limit of an immediately successive voltage pulse is greater than that of the one voltage pulse by a multiplier factor.
6. The method of claim 1 , wherein for each one of the voltage pulses, the amplitude of the voltage increases in discrete steps.
7. The method of claim 6 , wherein for each one of the voltage pulses, a number of the discrete steps exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
8. The method of claim 1 , wherein for each one of the voltage pulses, a duration of the one voltage pulse exceeds that of any of the plurality of voltage pulses preceding the one pulse.
9. The method of claim 1 , wherein all of the plurality of voltage pulses have a same duration.
10. The method of claim 1 , wherein for each one of the voltage pulses, the amplitude of the voltage increases gradually.
11. The method of claim 10 , wherein for each one of the voltage pulses, the gradual increase of the voltage amplitude is at a rate that exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
12. The method of claim 10 , wherein for each one of the voltage pulses, the gradual increase of the voltage amplitude is at a rate that is the same as that of all of the others of the plurality of voltage pulses.
13. The method of claim 2 , wherein for each one of the voltage pulses, the one voltage pulse has a beginning voltage amplitude that is equal to an ending voltage amplitude of any of the plurality of voltage pulses immediately preceding the one voltage pulse.
14. The method of claim 1 , wherein each of the voltage pulses ends with a voltage of reverse polarity.
15. The method of claim 1 , further comprising:
measuring a resistance of the metal oxide material after each of the plurality of voltage pulses; and
ceasing the applying of the voltage pulses in response to the measured resistance being below a predetermined threshold.
16. The method of claim 1 , further comprising:
ceasing the applying of the voltage pulses in response to an electrical current applied across the first and second electrodes during one of the voltage pulses exceeding a predetermined value.
17. A memory device comprising:
a metal oxide material disposed between and in electrical contact with first and second conductive electrodes;
a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes;
wherein for each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
18. The memory device of claim 17 , wherein for each one of the voltage pulses, a maximum of the amplitude exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
19. The memory device of claim 17 , wherein the voltage source is further configured to, for each of the voltage pulses, limit electrical current applied across the first and second electrodes during the voltage pulse to a current limit.
20. The memory device of claim 19 , wherein for each one of the voltage pulses, the current limit exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
21. The memory device of claim 20 , wherein for each one of the voltage pulses, the current limit of an immediately successive voltage pulse is greater than that of the one voltage pulse by a multiplier factor.
22. The memory device of claim 17 , wherein for each one of the voltage pulses, the amplitude of the voltage increases in discrete steps.
23. The memory device of claim 22 , wherein for each one of the voltage pulses, a number of the discrete steps exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
24. The memory device of claim 17 , wherein for each one of the voltage pulses, a duration of the one voltage pulse exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
25. The memory device of claim 17 , wherein all of the plurality of voltage pulses have a same duration.
26. The memory device of claim 17 , wherein for each one of the voltage pulses, the amplitude of the voltage increases gradually.
27. The memory device of claim 26 , wherein for each one of the voltage pulses, the gradual increase of the voltage amplitude is at a rate that exceeds that of any of the plurality of voltage pulses preceding the one voltage pulse.
28. The memory device of claim 26 , wherein for each one of the voltage pulses, the gradual increase of the voltage amplitude is at a rate that is the same as that of all of the others of the plurality of voltage pulses.
29. The memory device of claim 18 , wherein for each one of the voltage pulses, the one voltage pulse has a beginning voltage amplitude that is equal to an ending voltage amplitude of any of the plurality of voltage pulses immediately preceding the one voltage pulse.
30. The memory device of claim 17 , wherein each of the voltage pulses ends with a voltage of reverse polarity.
31. The memory device of claim 17 , further comprising:
a resistance detector for measuring a resistance of the metal oxide material after each of the plurality of voltage pulses, wherein the voltage source is configured to cease the applying of the voltage pulses in response to the measured resistance being below a predetermined threshold.
32. The memory device of claim 17 , wherein the voltage source is configured to cease the applying of the voltage pulses in response an electrical current applied across the first and second electrodes during one of the voltage pulses exceeding a predetermined value.