Latching current sensing amplifier for memory array
A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.
1. A circuit, comprising:
a first pair of p-type transistors (PFETs) connected in series;
a second pair of PFETs connected in series;
a transistor that shorts gates of the first pair of PFETs and gates of the second pair of PFETs in a sensing mode and separates the gates of the first pair of PFETs and the gates of the second pair of PFETs in a latching mode;
a first PFET of the first pair of PFETs and a second PFET of the second pair of PFETs are cross coupled by a common node in the latching mode; and
a second PFET of the first pair of PFETs and a first PFET of the second pair of PFETs are cross coupled by the common node in the latching mode.
2. The circuit of claim 1 , wherein the first pair of PFETs and the second pair of PFETs form a self-biased circuit.
3. The circuit of claim 1 , wherein the first pair of PFETs is connected between Vdd and a MID node and the second pair of PFETs is connected between Vdd and an OUT_ANALOG node.
4. The circuit of claim 1 , wherein each of the first pair of PFETs and the second pair of PFETs further comprises an output drain node, an intermediate node, and an input source node.
5. The circuit of claim 4 , wherein the input source node of the first pair of PFETs and the input source node of the second pair of PFETs are coupled to Vdd.
6. The circuit of claim 1 , wherein a true bitline (BLT) and a complementary bitline (BLC) of a differential memory cell are coupled at an intermediate node between PFETs of the first pair of PFETs and the second pair of PFETs, respectively.
7. The circuit of claim 6 , wherein the first pair of series connected PFETs and the second pair of series connected PFETs are each coupled in series to stacked transistors which pull a differential current from the differential memory cell through the BLT and BLC to OUT_ANALOG.
8. The circuit of claim 6 , wherein a current is injected into the differential memory cell through the BLT and the BLC from a first PFET of the first pair of PFETs and the second pair of PFETs, respectively.
9. The circuit of claim 1 , wherein a common-gate node for each of the first pair of PFETs and the second pair of PFETs is coupled together to an output-drain node in the sensing mode, and separated and reconfigured in a cross-coupled arrangement in the latching mode.
10. A circuit, comprising:
a first pair of p-type transistors (PFETs) connected in series;
a second pair of PFETs connected in series;
a first PFET of the first pair of PFETs and a second PFET of the second pair of PFETs are cross coupled by a common node; and
a second PFET of the first pair of PFETs and a first PFET of the second pair of PFETs are cross coupled by the common node,
wherein:
a true bitline (BLT) and a complementary bitline (BLC) of a differential memory cell are coupled at an intermediate node between PFETs of the first pair of PFETs and the second pair of PFETs, respectively,
a current is injected into the differential memory cell through the BLT and the BLC from a first PFET of the first pair of PFETs and the second pair of PFETs, respectively, and
a common-gate node for each of the first pair of PFETs and the second pair of PFETs is coupled together to an output-drain node in a sense mode, and separated and reconfigured in a cross-coupled arrangement in a latch mode.
11. The circuit of claim 10 , wherein the common-gate node, when enabled by a sense signal, will selectively short gates of the first pair of PFETs to gates of the second pair of PFETs.
12. The circuit of claim 10 , further comprising an isolation device configured to isolate the first pair of series connected PFETs and the second pair of series connected PFETs from the differential memory cell.
13. The circuit of claim 12 , wherein the isolation device is configured to isolate the first pair of series connected PFETs and the second pair of series connected PFETs from the differential memory cell only in response to a mode being the latch mode.
14. The circuit of claim 12 , wherein the BLT and the BLC are connected to the differential memory cell.
15. The circuit of claim 14 , wherein the isolation device is configured to isolate the first pair of series connected PFETs and the second pair of series connected PFETs from the BLT and the BLC only in response to a mode being the latch mode.
16. A method comprising:
injecting a first pair of currents into a true bitline (BLT) and a complement bitline (BLC) connected to a storage cell, wherein the first pair of currents is self biased;
drawing a second pair of currents out of the BLT and the BLC to provide gain and a voltage output; and
once initial current sensing is complete, disconnecting the self-bias by a transistor in response to a change in a sensing signal and latching two pairs of transistors by a common node in response to a change in a latching signal to form a cross-coupled latch,
wherein the sensing and latching is controlled by a single digital input, and signal margining is done by differential adjustment of the second pair of currents.
17. The method of claim 16 , further comprising:
coupling together common-gate nodes for each of the two pairs of transistors to an output-drain node during the initial current sensing; and
once the initial current sensing is complete, separating and reconfiguring the common-gate nodes in a cross-coupled arrangement.
18. The method of claim 16 , wherein the transistor shorts gates of each of the two pairs of transistors during the initial current sensing.
19. The method of claim 16 , wherein the disconnecting the self-bias once the initial current sensing is complete comprises the transistor separating gates of each of the two pairs of transistors.