IP Library Granted Patent US 10,593,602
Granted Patent B2
US 10,593,602 · App. 15/964,484 · Granted Mar 17, 2020

Semiconductor substrate crack mitigation systems and related methods

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Quick Facts
Patent No.
US 10,593,602
App. No.
15/964,484
Granted
Mar 17, 2020
Kind
B2
Abstract

Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.

Claims (35)

1. A method for healing a crack in a semiconductor substrate, the method comprising:

identifying a crack in a semiconductor substrate;

heating an area of the semiconductor substrate comprising the crack until the crack is healed;

electronically identifying the heated area of the semiconductor substrate;

processing the semiconductor substrate;

forming a plurality of semiconductor die in at least a portion of the semiconductor substrate; and

excluding semiconductor die formed in the heated area of the semiconductor substrate from further functional use.

2. The method of claim 1 , wherein the semiconductor substrate comprises silicon carbide.

3. The method of claim 1 , further comprising forming a same crystal orientation of the heated area of the semiconductor substrate as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the semiconductor substrate.

4. The method of claim 1 , further comprising forming a different crystal orientation of the heated area of the semiconductor substrate as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the semiconductor substrate.

5. The method of claim 1 , wherein a laser is used to heat an area of the semiconductor substrate.

6. The method of claim 1 , further comprising electronically identifying the area of the semiconductor substrate comprising the crack and only heating substantially the area of the semiconductor substrate electronically identified.

7. A method for mitigating propagation of a crack in a semiconductor substrate, the method comprising:

identifying a crack in a semiconductor substrate;

removing a portion of the semiconductor substrate comprising the crack;

coupling the semiconductor substrate to a carrier substrate;

completing the processing of the semiconductor substrate while coupled to the carrier substrate; and

forming a plurality of semiconductor die therefrom.

8. The method of claim 7 , wherein the semiconductor substrate comprises silicon carbide.

9. The method of claim 7 , wherein removing a portion of the semiconductor substrate comprises etching the portion of the semiconductor substrate.

10. The method of claim 7 , wherein removing a portion of the semiconductor substrate comprises polishing a sidewall of the semiconductor substrate.

11. The method of claim 7 , further comprising electronically identifying the removed portion of the semiconductor substrate, processing the semiconductor substrate, and forming a plurality of semiconductor die from a portion of the semiconductor substrate excluding the removed portion of the semiconductor substrate.

12. A method for healing a crack in a boule, the method comprising:

identifying a crack in a boule; and

heating an area of the boule comprising the crack until the crack is healed.

13. The method of claim 12 , wherein the boule comprises silicon carbide.

14. The method of claim 12 , further comprising electronically identifying the heated area of the boule, processing of the boule, and forming a plurality of semiconductor substrates from the boule.

15. The method of claim 12 , further comprising forming a same crystal orientation of the heated area of the boule as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled cooling and controlled heating of the heated area of the boule.

16. The method of claim 12 , further comprising forming a different crystal orientation of the heated area of the boule as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the boule.

17. The method of claim 12 , wherein a laser is used to heat an area of the boule.

18. The method of claim 12 , further comprising electronically identifying the area of the boule comprising the crack and only heating the area of the boule electronically identified.

19. A method for identifying damaged semiconductor die comprising:

identifying an area comprising a crack in one of a boule and semiconductor substrate;

electronically marking the area; and

processing one of the boule and semiconductor substrate into a plurality of semiconductor die while excluding semiconductor die from the marked area of one of the boule and semiconductor substrate from further processing following singulation of the plurality of semiconductor die.

Assignments (4)
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047864, FRAME 0611 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064077/0298 →
PATENT SECURITY AGREEMENT Recorded Oct 16, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047864/0611 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2018
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 045654/0036 →