Remote contacts for a trench semiconductor device and methods of manufacturing semiconductor devices

1. A semiconductor device structure, comprising:

a region of semiconductor material comprising a first conductivity type, a first major surface, and a second major surface opposite to the first major surface;

a first trench gate structure comprising:

a first trench extending from the first major surface into the region of semiconductor material;

a first dielectric structure over sidewall surfaces and a portion of a lower surface of the first trench, wherein the first dielectric structure comprises a first opening adjacent to the lower surface of the first trench;

a first recessed contact extending through the first opening; and

a first contact region over the first recessed contact within the first trench, wherein the first recessed contact and the first contact region comprise different materials;

a first doped region comprising a second dopant conductivity type opposite to the first conductivity type in the region of semiconductor material spaced apart from the first major surface and below the first trench; and

a gate contact region in the region of semiconductor material electrically coupled to the first doped region, wherein:

the gate contact region comprises a second doped region of the second conductivity type; and

the first doped region and the second doped region contact at a side of the second doped at a location below the first major surface.

2. The structure of claim 1 , further comprising:

a second contact region electrically coupled to gate contact region; and

a conductive layer electrically coupled to the first contact region and the second contact region, wherein:

the first contact region and the second contact region comprise a Schottky barrier material.

3. The structure of claim 1 , wherein:

portions of the first recessed contact are electrically coupled to the first doped region through the opening in the first dielectric structure.

4. The structure of claim 1 , wherein:

portions of the first recessed contact are electrically decoupled from the first doped region.

5. The structure of claim 1 , wherein:

the second doped region is a patterned region within a discrete portion of the region of semiconductor material laterally adjacent to the first gate trench structure.

6. The structure of claim 1 , further comprising:

dielectric spacers along sidewall surfaces of the first dielectric structure, wherein:

the dielectric spacers are interposed between the first dielectric structure and the first contact region.

7. The structure of claim 6 , further comprising:

a conductive layer electrically coupled to the first contact region, wherein:

the conductive layer contacts the first contact region at a location above a lower surface of the first trench.

8. The structure of claim 1 , wherein:

the first recessed contact comprises a polycrystalline semiconductor material; and

the first contact region comprises a Schottky barrier material.

9. The structure of claim 8 , wherein:

the polycrystalline semiconductor material is an intrinsic material.

10. The structure of claim 8 , wherein the polycrystalline semiconductor material is lightly doped to have a dopant concentration less than about 1.0×10 18 atoms/cm 3 .

11. The structure of claim 1 , wherein:

the region of semiconductor material comprises:

a substrate; and

a semiconductor layer over the substrate;

the semiconductor layer defines the first major surface; and

the semiconductor layer has a dopant profile that changes over its depth inward from the first major surface.

12. The structure of claim 11 , wherein:

the semiconductor layer has a plurality of regions; and

each region has a different dopant concentration.

13. The structure of claim 1 , wherein:

the first doped region laterally overlaps into the gate contact region.

14. The structure of claim 1 , wherein:

the gate contact region extends into the region of semiconductor material to a depth that is greater than that of the first doped region.

15. A semiconductor device structure, comprising:

a region of semiconductor material comprising an active region, a first conductivity type, a first major surface, and a second major surface opposite to the first major surface;

trench gate structures comprising:

trenches extending from the first major surface into the region of semiconductor material;

first dielectric structures over sidewall surfaces and a portion of a lower surface of each trench, wherein each first dielectric structure comprises an opening adjacent to the lower surface;

recessed contacts extending through the openings; and

first contact regions over the recessed contacts within the trenches, wherein the recessed contacts and the first contact regions comprise different materials;

doped regions comprising a second dopant conductivity type opposite to the first conductivity type in the region of semiconductor material spaced apart from the first major surface and below the trenches; and

gate contact regions in the active region of region of semiconductor material electrically coupled to the doped regions, wherein:

at least first portions of the recessed contacts are electrically coupled to the doped regions; and

the first contact regions comprise a Schottky barrier material.

16. The structure of claim 15 , wherein:

the recessed contacts are a lightly doped material with a dopant concentration less than about 1.0×10 18 atoms/cm 3 .

17. The structure of claim 15 , wherein:

the recessed contacts are an intrinsic material.

18. The structure of claim 15 , wherein:

the doped regions laterally extend into the gate contact regions.

19. The structure of claim 15 , wherein:

the doped regions each have a first lateral width;

the trench gate structures each have a second lateral width; and

the second lateral width is greater than the first lateral width.

20. A method of forming a semiconductor device comprising:

providing a region of semiconductor material comprising an active region, a first conductivity type, a first major surface, and a second major surface opposite to the first major surface;

providing trench gate structures comprising:

trenches extending from the first major surface into the region of semiconductor material;

first dielectric structures over sidewall surfaces and a portion of a lower surface of each trench, wherein each first dielectric structure comprises an opening adjacent to the lower surface;

recessed contacts extending through the openings; and

first contact regions over the recessed contacts within the trenches, wherein the recessed contacts and the first contact regions comprise different materials;

providing doped regions comprising a second dopant conductivity type opposite to the first conductivity type in the region of semiconductor material spaced apart from the first major surface and below the trenches; and

providing gate contact regions in the active region of region of semiconductor material electrically coupled to the doped regions, wherein:

at least first portions of the recessed contacts are electrically coupled to the doped regions.