IP Library Granted Patent US 11,670,618
Granted Patent B2
US 11,670,618 · App. 17/008,918 · Granted Jun 6, 2023

System-in-package with double-sided molding

Inventors: DeokKyung Yang (Incheon Si, KR); YongMin Kim (Incheon-si, KR); JaeHyuk Choi (Incheon, KR); YeoChan Ko (Incheon, KR); HeeSoo Lee (Kyunggi-do, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L25/0655H01L21/56H01L21/561H01L21/565H01L21/566H01L21/6835H01L23/3121H01L23/552H01L25/0652H01L25/16H01L25/50H01L21/486H01L22/14H01L23/3128H01L23/49816H01L23/50H01L23/5384H01L24/05H01L24/11H01L24/13H01L24/81H01L24/94H01L2221/68331H01L2221/68345H01L2221/68359H01L2221/68381H01L2224/0345H01L2224/03452H01L2224/03462H01L2224/03464H01L2224/0401H01L2224/05111H01L2224/05124H01L2224/05139H01L2224/05144H01L2224/05147H01L2224/05155H01L2224/05611H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/1132H01L2224/1145H01L2224/11334H01L2224/11462H01L2224/11464H01L2224/11849H01L2224/11901H01L2224/131H01L2224/13111H01L2224/13113H01L2224/13116H01L2224/13124H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/16113H01L2224/16227H01L2224/32225H01L2224/73204H01L2224/81005H01L2224/81191H01L2224/81192H01L2224/81201H01L2224/81203H01L2224/81411H01L2224/81424H01L2224/81439H01L2224/81444H01L2224/81447H01L2224/81455H01L2224/81466H01L2224/81484H01L2224/81815H01L2224/92125H01L2224/94H01L2224/97H01L2225/06517H01L2225/06537H01L2225/06572H01L2924/0105H01L2924/01013H01L2924/01022H01L2924/01028H01L2924/01029H01L2924/01047H01L2924/01074H01L2924/01079H01L2924/15311H01L2924/15312H01L2924/18161H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2924/19106H01L2924/3025
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Quick Facts
Patent No.
US 11,670,618
App. No.
17/008,918
Granted
Jun 6, 2023
Kind
B2
Abstract

A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

Claims (47)

1. A method of making a semiconductor device, comprising:

providing a substrate including an opening formed through the substrate;

disposing the substrate in a mold; and

depositing an encapsulant into the mold, wherein the encapsulant flows through the opening.

2. The method of claim 1 , further including:

disposing an interconnect structure on the substrate;

depositing the encapsulant over the interconnect structure; and

backgrinding the encapsulant to expose the interconnect structure.

3. The method of claim 1 , further including:

disposing a leadframe over the substrate, wherein the leadframe includes a base and a plurality of conductive pillars disposed between the base and the substrate;

depositing the encapsulant between the leadframe and substrate; and

removing the base to leave the conductive pillars exposed from the encapsulant.

4. The method of claim 1 , further including singulating the substrate after depositing the encapsulant, wherein the opening is removed.

5. The method of claim 1 , further including:

disposing the substrate in the mold with a portion of the mold contacting a portion of a first surface of the substrate;

removing the substrate and encapsulant from the mold;

disposing a mask over the portion of the first surface of the substrate;

forming a first shielding layer over the mask and first surface of the substrate; and

removing the mask and a portion of the first shielding layer.

6. The method of claim 5 , further including:

singulating the substrate and encapsulant; and

forming a second shielding layer over the encapsulant opposite the first shielding layer after singulating.

7. A method of making a semiconductor device, comprising:

providing a substrate including a plurality of device regions; and

forming a first opening through the substrate outside a footprint of the device regions, wherein the substrate remains extending completely around the first opening.

8. The method of claim 7 , wherein the first opening includes a length greater than a combined length of a plurality of the device regions.

9. The method of claim 7 , further including forming the first opening at an edge of the substrate.

10. The method of claim 9 , further including forming a second opening between two of the plurality of device regions.

11. The method of claim 7 , further including forming the first opening between two of the plurality of device regions.

12. The method of claim 7 , further including disposing a first electronic component on a first surface of the substrate within a first device region of the plurality of device regions.

13. The method of claim 12 , further including disposing a second electronic component on a second surface of the substrate within the first device region of the plurality of device regions.

14. A semiconductor device, comprising:

a substrate including a plurality of device regions; and

a first opening formed through the substrate near an edge of the substrate, wherein the substrate extends completely around the first opening.

15. The semiconductor device of claim 14 , wherein the device regions are organized into a plurality of columns and the first opening extends across each of the plurality of columns.

16. The semiconductor device of claim 14 , further including a plurality of first openings formed at the edge of the substrate.

17. The semiconductor device of claim 14 , further including a second opening formed between two of the plurality of device regions.

18. The semiconductor device of claim 14 , further including a first electronic component disposed on a first surface of the substrate within a first device region of the plurality of device regions.

19. The semiconductor device of claim 18 , further including a second electronic component disposed on a second surface of the substrate within the first device region of the plurality of device regions.

20. A semiconductor device, comprising:

a substrate including a plurality of device regions; and

an opening formed through the substrate outside a footprint of the device regions, wherein the substrate extends completely around the first opening.

21. The semiconductor device of claim 20 , wherein the device regions are organized into a plurality of columns and the opening extends across each of the plurality of columns.

22. The semiconductor device of claim 20 , wherein the opening is formed at an edge of the substrate.

23. The semiconductor device of claim 20 , wherein the opening is formed between two of the plurality of device regions.

24. The semiconductor device of claim 20 , further including a first electronic component disposed on a first surface of the substrate within a first device region of the plurality of device regions.

25. The semiconductor device of claim 24 , further including a second electronic component disposed on a second surface of the substrate within the first device region of the plurality of device regions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2020
From: YANG, DEOKKYUNG; KIM, YONGMIN; CHOI, JAEHYUK; KO, YEOCHAN; LEE, HEESOO
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 053658/0391 →
Continuity (3)
Continuation 16826169 · Mar 21, 2020
Continuation 15458649 · Mar 14, 2017
Related Publication 20200402955A1 · Dec 24, 2020
Cited By (1)
US 12,469,754