IP Library Patent Application 17077145
Patent Application
App. No. 17/077,145

QUAD FLAT NO LEADS PACKAGE WITH LOCKING FEATURE

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Quick Facts
Patent No.
US None
App. No.
17/077,145
Filed
Oct 22, 2020
Examiner
KIM, SU C
Art Unit
2899
USPC
257/666
Abstract

Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

Claims (34)

1 . A method for forming a semiconductor package, the method comprising:

providing a lead frame comprising at least one lead positioned at an outer edge of the package;

etching one half of a first portion of the at least one lead at an outer edge of the at least one lead adjacent to the outer edge of the package; and

etching one half of a second portion of the at least one lead at an inner edge of the at least one lead opposite the outer edge of the at least one lead;

wherein the first portion is configured to mechanically lock with a mold compound of the package; and

wherein the second portion is a portion of the at least one lead that contacts a mounting surface of the semiconductor package.

2 . The method of claim 1 , wherein the mounting surface extends to the outer edge of the package.

3 . The method of claim 1 , wherein the first portion of the at least one lead is configured to have space for coupling a wire bond thereto.

4 . The method of claim 1 , further comprising a second lead adjacent to the at least one lead where the second lead and the at least one lead have a lead pitch of at least 0.2 millimeters.

5 . The method of claim 1 , wherein the at least one lead is a corner lead positioned where two outer edges of the package meet.

6 . The method of claim 5 , wherein the second portion is located on two outer edges of the package.

7 . A method for forming a semiconductor package, the method comprising:

providing a lead frame comprising a corner lead positioned at an outer edge of the package;

etching one half of a first portion of the corner lead at an outer edge of the corner lead adjacent to the outer edge of the package; and

etching one half of a second portion of the corner lead at an inner edge of the corner lead opposite the outer edge of the corner lead;

wherein the first portion is configured to mechanically lock with a mold compound of the package; and

wherein the second portion extends to the outer edge of the package.

8 . The method of claim 7 , wherein the second portion forms a mounting surface positioned where two outer edges of the package meet.

9 . The method of claim 7 , wherein the first portion of the corner lead is configured to have space for coupling a wire bond thereto.

10 . The method of claim 7 , further comprising a second lead adjacent to the corner lead where the second lead and the corner lead have a lead pitch of at least 0 . 2 millimeters.

11 . The method of claim 7 , wherein the corner lead is positioned where two outer edges of the package meet.

12 . The method of claim 11 , wherein the second portion is located on two outer edges of the package.

13 . A method for forming a semiconductor package, the method comprising:

providing a lead frame comprising a lead positioned where two outer edges of the package meet;

etching one half of a first portion of the lead at an outer edge of the lead adjacent to at least one of the two outer edges of the package; and

etching one half of a second portion of the lead at an inner edge of the lead opposite the at least one outer edge of the lead;

wherein the first portion is configured to mechanically lock with a mold compound of the package;

wherein the second portion is a portion of the lead that contacts a mounting surface of the semiconductor package; and

wherein the mounting surface extends to at least one of the two outer edges of the package.

14 . The method of claim 13 , wherein the mounting surface extends to two outer edges of the package.

15 . The method of claim 13 , wherein the first portion of the lead is configured to have space for coupling a wire bond thereto.

16 . The method of claim 13 , further comprising a second lead adjacent to the lead where the second lead and the at least one lead have a lead pitch of at least 0.2 millimeters.

17 . The method of claim 13 , wherein the lead is a corner lead.

18 . The method of claim 17 , wherein the second portion is located on two outer edges of the package.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2020
From: WANG, SOON WEI; LIEW, HOW KIAT; PALAGUD, JOSE FELIXMINIA, JR.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054136/0995 →