COMPARATOR SYSTEM HAVING INTERNAL INPUT OFFSET VOLTAGE
Implementations of a comparator system may include a first transistor including a gate where the gate is configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor. The first transistor may be included in a PMOS differential pair. A first offset resistor may be coupled to the source of the first transistor and to a source of a second transistor included in the PMOS differential pair. A second offset resistor may be coupled between the first transistor and the second transistor. A voltage difference between a first back gate bias voltage of the first transistor and a second back gate bias voltage of the second transistor may indicate a current value through the resistor.
1 . A comparator system comprising:
a transistor comprising a gate, the gate configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor, the transistor comprised in a first cascode device coupled with a second cascode device;
a first offset resistor coupled to a source of the first cascode device and a source of the second cascode device;
a second offset resistor coupled between the cascode tail current source of the first cascode device and the second cascode device;
a first one or more switches coupled between the first cascode device and the second cascode device; and
a second one or more switches coupled between the second offset resistor and the first cascode device.
2 . The system of claim 1 , wherein a resistance of the first offset resistor is changed using the first one or more switches.
3 . The system of claim 1 , wherein a resistance of the second offset resistor is changed to equal the resistance of the first offset resistor using the second one or more switches.
4 . The system of claim 1 , further comprising two additional transistors operatively coupled together.
5 . The system of claim 1 , further comprising a common ground coupled with the first cascode device and the second cascode device.
6 . The system of claim 1 , wherein the first offset resistor is configured to generate an input offset voltage.
7 . The system of claim 1 , wherein there is no offset voltage resulting from the RC noise filter.
8 . A comparator system comprising:
a transistor comprising a gate, the gate configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor, the transistor comprised in a first cascode device coupled with a second cascode device;
a first offset resistor coupled to a source of the first cascode device and a source of the second cascode device;
a second offset resistor coupled between the cascode tail current source of the first cascode device and the second cascode device;
a first two switches coupled between the first cascode device and the second cascode device; and
a second two switches coupled between the second offset resistor and the first cascode device.
9 . The system of claim 8 , wherein a resistance of the first offset resistor is changed using the first two switches.
10 . The system of claim 8 , wherein a resistance of the second offset resistor is changed to equal the resistance of the first offset resistor using the second two switches.
11 . The system of claim 8 , further comprising two additional transistors operatively coupled together.
12 . The system of claim 8 , further comprising a common ground coupled with the first cascode device and the second cascode device.
13 . The system of claim 8 , wherein the first offset resistor is configured to generate an input offset voltage.
14 . The system of claim 8 , wherein there is no offset voltage resulting from the RC noise filter.
15 . A comparator system comprising:
a transistor comprising a gate, the gate configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor, the transistor comprised in a first cascode device coupled with a second cascode device;
a first two offset resistors coupled to a source of the first cascode device and a source of the second cascode device;
a second two offset resistors coupled between the cascode tail current source of the first cascode device and the second cascode device;
a first two switches coupled between the first cascode device and the second cascode device; and
a second two switches coupled between the second offset resistor and the first cascode device.
16 . The system of claim 15 , wherein a combined resistance of the first two offset resistors is changed using the first two switches.
17 . The system of claim 15 , wherein a combined resistance of the second two offset resistors is changed to equal a combined resistance of the first two offset resistors using the second two switches.
18 . The system of claim 15 , further comprising two additional transistors operatively coupled together.
19 . The system of claim 15 , wherein the first two offset resistors is configured to generate an input offset voltage.
20 . The system of claim 15 , wherein there is no offset voltage resulting from the RC noise filter.