Dual-way sensing scheme for better neighboring word-line interference
A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.
1 . A storage device, comprising:
a non-volatile memory, the non-volatile memory including a block of N wordlines partitioned into a plurality of sub-blocks, the plurality of sub-blocks including an upper sub-block of a first subset of the block of N wordlines and located on a drain side of the block and including a lower sub-block of a second subset of the block of N wordlines and located on a source side of the block; and
control circuitry coupled to the block of N wordlines and configured to:
perform a program operation in a normal order programming sequence on the first upper sub-block;
perform a sensing operation on the upper sub-block using a reverse sensing scheme, the reverse sensing scheme including charging a first sense capacitor with current conducted through a first NAND string and a first bit line then analyzing a potential of the first sense capacitor after charging is completed;
perform a program operation in a reverse order programming sequence on the lower sub-block; and
perform a sensing operation on the lower sub-block using a regular sensing scheme, the regular sensing scheme including discharging the first sense capacitor through the first bit line and then through the first NAND string and then analyzing a potential of the first sense capacitor after discharging is completed.
2 . The storage device of claim 1 , wherein the upper sub-block is an upper tier sub-block of the block.
3 . The storage device of claim 1 , wherein the lower sub-block is a lower tier sub-block of the block.
4 . The storage device of claim 1 , wherein the plurality of sub-blocks include a middle sub-block of a third subset of the block of N wordlines and the control circuitry is further configured to:
perform a program operation in a normal order programming sequence on the third middle sub-block; and
perform a sensing operation on the middle sub-block using a reverse sensing scheme.
5 . The storage device of claim 1 , wherein the plurality of sub-blocks include a middle sub-block of a third subset of the block of N wordlines and the control circuitry is further configured to:
perform a program operation in a reverse order programming sequence on the middle sub-block; and
perform a sensing operation on the middle sub-block using a normal sensing scheme.
6 . The storage device of claim 1 , wherein a same sensing circuit is used to perform the sensing operation using the regular sensing scheme and perform the sensing operation using the reverse sensing scheme.
7 . The storage device of claim 1 , wherein the second subset of the block of N wordlines is different than the first subset of the block of N wordlines.
8 . A method of operating a non-volatile semiconductor memory device, the non-volatile semiconductor memory device including a block of N wordlines partitioned into a plurality of sub-blocks, the plurality of sub-blocks including a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines, and the method comprising:
performing a program operation in a normal order programming sequence on the first sub-block;
performing a sensing operation on the first sub-block using a reverse sensing scheme, the reverse sensing scheme including charging a first sense capacitor using current conducted through a first NAND string and a first bit line and then analyzing a potential of the at least one sense capacitor after charging is completed;
performing a program operation in a reverse order programming sequence on the second sub-block; and
performing a sensing operation on the second sub-block using a regular sensing scheme, the regular sensing scheme including discharging the first sense capacitor through the first bit line and through the first NAND string and then analyzing a potential of the at least one sense capacitor after charging is completed.
9 . The method of claim 8 , wherein the first sub-block is an upper tier sub-block of the block.
10 . The method of claim 8 , wherein the second sub-block is a lower tier sub-block of the block.
11 . The method of claim 8 , wherein the plurality of sub-blocks include a third sub-block of a third subset of the block of N wordlines and the method further comprises:
performing a program operation in a normal order programming sequence on the third sub-block; and
performing a sensing operation on the third sub-block using a reverse sensing scheme.
12 . The method of claim 8 , wherein the plurality of sub-blocks include a third sub-block of a third subset of the block of N wordlines and the method further comprises:
performing a program operation in a reverse order programming sequence on the third sub-block; and
performing a sensing operation on the third sub-block using a normal sensing scheme.
13 . The method of claim 8 , wherein a same sensing circuit is used to perform the sensing operation using the regular sensing scheme and perform the sensing operation using the reverse sensing scheme.
14 . The method of claim 8 , wherein the second subset of the block of N wordlines is different than the first subset of the block of N wordlines.
15 . An apparatus comprising:
means for performing a program operation in a normal order programming sequence on a first sub-block of a block of a non-volatile memory;
means for performing a sensing operation on the first sub-block using a reverse sensing scheme, the reverse sensing scheme including charging a first sense capacitor with current conducted through a first NAND string and a first bit line and then analyzing a potential of the at least one sense capacitor after charging is completed;
means for performing a program operation in a reverse order programming sequence on a second sub-block of the block; and
means for performing a sensing operation on the second sub-block using a regular sensing scheme, the regular sensing scheme including discharging the at least one sense capacitor through the first bit line and the first NAND string and then analyzing a potential of the at least one sense capacitor after discharging is completed.
16 . The apparatus of claim 15 , wherein the first sub-block is an upper tier sub-block of the block.
17 . The apparatus of claim 15 , wherein the second sub-block is a lower tier sub-block of the block.
18 . The apparatus of claim 15 , further comprising:
means for performing a program operation in a normal order programming sequence on a third sub-block of the block; and
means for performing a sensing operation on the third sub-block using a reverse sensing scheme.
19 . The apparatus of claim 15 , further comprising:
means for performing a program operation in a reverse order programming sequence on a third sub-block of the block; and
means for performing a sensing operation on the third sub-block using a normal sensing scheme.
20 . The apparatus of claim 19 , wherein the third sub-block is a middle sub-block of the block.