Ultra-low power adaptively reconfigurable system
Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.
1. An integrated circuit (IC) comprising:
a logic circuit;
a plurality of reconfigurable analog circuits; and
a first interface to receive a first input signal, and
wherein the IC is configured to:
in a first IC configuration, process the first input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first IC configuration; and
change, responsive to the logic circuit determining that the first output value is within a range between a first threshold condition for reconfiguring the IC and a second threshold condition for waking-up a central processing unit (CPU), one or more of the plurality of reconfigurable analog circuits into a second IC configuration with a second configuration setting.
2. The IC of claim 1 , wherein the plurality of reconfigurable analog circuits have a higher operating power in the second IC configuration than in the first IC configuration.
3. The IC of claim 1 , wherein the IC further comprises:
a second interface to communicate with the CPU, and
wherein the IC is further configured to:
in the second IC configuration, process a second input signal through the plurality of reconfigurable analog circuits to generate a second output value, the plurality of reconfigurable analog circuits having the second configuration setting in the second IC configuration; and
responsive to the second output value satisfying the second threshold condition for waking-up the CPU, output, through the second interface, a wake-up signal to the CPU.
4. The IC of claim 3 , wherein the IC is further configured to:
responsive to outputting the wake-up signal to the CPU, receive, from the CPU, configuration data comprising a third configuration setting; and
reconfigure the plurality of reconfigurable analog circuits into a third IC configuration with the third configuration setting.
5. The IC of claim 1 , wherein the IC further comprises:
a second interface to communicate with the CPU, and
wherein the IC is further configured to:
in the second IC configuration, process a second input signal through the plurality of reconfigurable analog circuits to generate a second output value, the plurality of reconfigurable analog circuits having the second configuration setting in the second IC configuration; and
responsive to the second output value, output, through the second interface, a mode selection signal to the CPU.
6. The IC of claim 1 , wherein the IC further comprises a first set of one or more registers to store the first configuration setting and a second set of one or more registers to store the second configuration setting.
7. The IC of claim 1 , wherein the IC comprises a set of one or more registers to store the first configuration setting, and wherein to change the plurality of reconfigurable analog circuits into the second configuration, the IC is to:
modify contents of the set of one or more registers to store the second configuration setting; and
reconfigure at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.
8. The IC of claim 1 , wherein to change the one or more of the plurality of reconfigurable analog circuits into the second IC configuration, the logic circuit is to cause a reconfiguration of at least two of:
a continuous time block (CTB) that executes signal processing in a continuous time domain;
a discrete time block (DTB) that executes signal processing in a discrete time domain;
an analog-to-digital converter (ADC) circuit that process an output of at least one of the CTB or the DTB; or
one or more multiplexers that selectively connect the first interface to a plurality of inputs of at least of one of the CTB, the DTB, or the ADC circuit; or
an analog reference block that generates at least one of a voltage reference, a current reference, or a clock signal.
9. A system comprising:
an input/output (IO) device to receive a first input signal from a signal source;
a digital subsystem comprising a memory and a central processing unit (CPU) coupled to the memory;
an integrated circuit (IC) coupled to the IO device and to the digital subsystem, wherein the IC comprises:
a logic circuit, and
a plurality of reconfigurable analog circuits comprising, and
wherein the IC is configured to:
in a first IC configuration, process the first input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the first input signal, the plurality of reconfigurable analog circuits having a first configuration setting in the first IC configuration; and
change, responsive to the logic circuit determining that the first output value is within a range between a first threshold condition for reconfiguring the IC and a second threshold condition for waking-up the CPU, one or more of the plurality of reconfigurable analog circuits into a second IC configuration with a second configuration setting.
10. The system of claim 9 , wherein the plurality of reconfigurable analog circuits have a higher operating power in the second IC configuration than in the first IC configuration.
11. The system of claim 9 , wherein the IC is further configured to:
in the second IC configuration, process a second input signal through the plurality of reconfigurable analog circuits to generate a second output value, the plurality of reconfigurable analog circuits having the second configuration setting in the second IC configuration; and
responsive to the second output value satisfying the second threshold condition for waking-up the CPU, output a mode selection signal to the digital subsystem.
12. The system of claim 11 , wherein the IC is further configured to:
responsive to outputting the mode selection signal to the digital subsystem, receive, from the digital subsystem, configuration data comprising a third configuration setting, wherein the third configuration setting is different than the second configuration setting; and
reconfigure the plurality of reconfigurable analog circuits into a third IC configuration with the third configuration setting.
13. The system of claim 9 , wherein the IC comprises a first set of registers to store the first configuration setting and a second set of registers to store the second configuration setting.
14. The system of claim 9 , wherein the IC comprises a set of registers to store the first configuration setting, and wherein to reconfigure the plurality of reconfigurable analog circuits into the second configuration is to:
modify contents of the set of registers to store the second configuration setting; and
reconfigure at least one of the reconfigurable analog circuits according to the modified contents of the set of registers.
15. A method comprising:
receiving a first input signal by an integrated circuit (IC) via a first interface, the IC comprising a plurality of reconfigurable analog circuits and a logic circuit;
processing, with the IC in a first IC configuration, the first input signal through the plurality of reconfigurable analog circuits, wherein the plurality of reconfigurable analog circuits have a first configuration setting in the first IC configuration;
generating a first output value based on the first input signal; and
changing, responsive to the logic circuit determining that the first output value is between a first threshold condition for reconfiguring the IC and a second threshold condition for waking-up a central processing unit (CPU), one or more of the plurality of reconfigurable analog circuits into a second IC configuration with a second configuration setting.
16. The method of claim 15 , wherein the plurality of reconfigurable analog circuits have a higher operating power in the second IC configuration than in the first IC configuration.
17. The method of claim 15 , further comprising:
processing, with the IC in the second IC configuration, a second input signal through the plurality of reconfigurable analog circuits, wherein the plurality of reconfigurable analog circuits have the second configuration setting in the second IC configuration;
generating a second output value; and
responsive to the second output value, outputting, through the interface, a signal to a CPU communicatively coupled to the IC.
18. The method of claim 17 , wherein outputting the signal to the CPU is responsive to determining that the second output value meets the second threshold condition.
19. The method of claim 15 , wherein changing the one or more of the plurality of reconfigurable analog circuits into the second IC configuration, comprises the logic circuit causing a reconfiguration of at least two of:
a continuous time block (CTB) that executes signal processing in a continuous time domain;
a discrete time block (DTB) that executes signal processing in a discrete time domain;
an analog-to-digital converter (ADC) circuit that process an output of at least one of the CTB or the DTB; or
one or more multiplexers that selectively connect the interface to a plurality of inputs of at least of one of the CTB, the DTB, or the ADC circuit; or
an analog reference block that generates at least one of a voltage reference, a current reference, or a clock signal.