IP Library Granted Patent US 12,550,754
Granted Patent B2
US 12,550,754 · App. 18/154,722 · Granted Feb 10, 2026

Current sharing mismatch reduction in power semiconductor device modules

Inventors: Oseob Jeon (Seoul, KR); Seungwon Im (Bucheon, KR); Rajani Kumar Thirukoluri (Munich, DE); Roveendra Paul (Dublin, CA)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49562H01L23/5386H01L24/40H01L24/48H01L24/73H01L2224/40225H01L2224/48225H01L2224/73221
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Quick Facts
Patent No.
US 12,550,754
App. No.
18/154,722
Granted
Feb 10, 2026
Kind
B2
Abstract

In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.

Claims (105)

1 . A half-bridge circuit power module comprising:

a substrate including:

a first patterned metal layer disposed on a surface of the substrate;

a second patterned metal layer disposed on the surface of the substrate; and

a third patterned metal layer disposed on the surface of the substrate;

a first high-side transistor disposed on the first patterned metal layer;

a second high-side transistor disposed on the first patterned metal layer;

a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer;

a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer;

a first low-side transistor disposed on the second patterned metal layer;

a second low-side transistor disposed on the second patterned metal layer;

a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer; and

a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.

2 . The half-bridge circuit power module of claim 1 , wherein:

the first patterned metal layer is electrically coupled with a DC+ terminal of the half-bridge circuit power module;

the second patterned metal layer is electrically coupled with an output terminal of the half-bridge circuit power module;

the third patterned metal layer is electrically coupled with an DC− terminal of the half-bridge circuit power module.

3 . The half-bridge circuit power module of claim 2 , wherein:

the first conductive clip electrically couples a source terminal of the first high-side transistor with the output terminal;

the second conductive clip electrically couples a source terminal of the second high-side transistor with the output terminal;

the third conductive clip electrically couples a source terminal of the first low-side transistor with the DC− terminal; and

the fourth conductive clip electrically couples a source terminal of the second low-side transistor with the DC− terminal.

4 . The half-bridge circuit power module of claim 2 , wherein:

the DC+ terminal is a first DC+ terminal; and

the substrate further includes a fourth patterned metal layer disposed on the surface of the substrate, the fourth patterned metal layer being electrically coupled with a second DC+ terminal,

the half-bridge circuit power module further comprising:

a third high-side transistor having a drain terminal disposed on the fourth patterned metal layer;

a fourth high-side transistor having a drain terminal disposed on the fourth patterned metal layer;

a fifth conductive clip electrically coupling a source terminal of the third high-side transistor with the output terminal; and

a sixth conductive clip electrically coupling the fourth high-side transistor with the output terminal.

5 . The half-bridge circuit power module of claim 4 , wherein:

the first DC+ terminal is electrically coupled with the first patterned metal layer via a first conductive post; and

the second DC+ terminal is electrically coupled with the fourth patterned metal layer via a second conductive post.

6 . The half-bridge circuit power module of claim 4 , wherein:

the fifth conductive clip electrically couples the source terminal of the third high-side transistor with the output terminal via a fifth patterned metal layer disposed on the surface of the substrate.

7 . The half-bridge circuit power module of claim 5 , wherein the output terminal is:

electrically coupled with the second patterned metal layer via a first conductive post; and

electrically coupled with the fourth patterned metal layer via a second conductive post.

8 . The half-bridge circuit power module of claim 2 , wherein the substrate further includes a fourth patterned metal layer electrically coupled with the output terminal,

the half-bridge circuit power module further comprising:

a third low-side transistor disposed on the fourth patterned metal layer; and

a fourth low-side transistor disposed on the fourth patterned metal layer,

the third conductive clip further electrically coupling the third low-side transistor to the third patterned metal layer, and

the fourth conductive clip further electrically coupling the fourth low-side transistor to the third patterned metal layer.

9 . The half-bridge circuit power module of claim 8 , where the DC− terminal is electrically coupled to the third patterned metal layer via a conductive post, the conductive post being disposed between the third conductive clip and the fourth conductive clip.

10 . The half-bridge circuit power module of claim 8 , further comprising:

a fifth low-side transistor disposed on the first patterned metal layer;

a sixth low-side transistor disposed on the fourth patterned metal layer;

a seventh low-side transistor disposed on the first patterned metal layer; and

an eighth low-side transistor disposed on the fourth patterned metal layer;

the third conductive clip further electrically coupling the fifth low-side transistor and the sixth low-side transistor to the third patterned metal layer, and

the fourth conductive clip further electrically coupling the sixth low-side transistor and the seventh low-side transistor to the third patterned metal layer.

11 . The half-bridge circuit power module of claim 1 , wherein:

respective drain terminals of the first high-side transistor and the second high-side transistor are disposed on and electrically coupled with the first patterned metal layer; and

respective drain terminals of the first low-side transistor and the second low-side transistor are disposed on and electrically coupled with the second patterned metal layer.

12 . A half-bridge circuit power module comprising:

a substrate including:

a first patterned metal layer disposed on a surface of the substrate and electrically coupled with an output terminal;

a second patterned metal layer disposed on the surface of the substrate and electrically coupled with a DC− terminal;

a third patterned metal layer disposed on the surface of the substrate and electrically coupled with the output terminal;

a first low-side transistor disposed on the first patterned metal layer;

a second low-side transistor disposed on the first patterned metal layer;

a third low-side transistor disposed on the third patterned metal layer;

a fourth low-side transistor disposed on the third patterned metal layer;

a conductive clip electrically coupling the first low-side transistor, the second low-side transistor, the third low-side transistor and the fourth low-side transistor with the second patterned metal layer.

13 . The half-bridge circuit power module of claim 12 , wherein:

the conductive clip includes an opening through which the second patterned metal layer is exposed; and

the DC− terminal is electrically coupled with the second patterned metal layer via a conductive post disposed within the opening of the conductive clip.

14 . The half-bridge circuit power module of claim 12 , wherein:

the output terminal is coupled with the first patterned metal layer via a first conductive post; and

the output terminal is coupled with the third patterned metal layer via a second conductive post.

15 . The half-bridge circuit power module of claim 12 , wherein the substrate further includes:

a fourth patterned metal layer disposed on the surface of the substrate; and

a fifth patterned metal layer disposed on the surface of the substrate;

the half-bridge circuit power module further comprising:

a first high-side transistor disposed on the fourth patterned metal layer;

a second high-side transistor disposed on the fourth patterned metal layer;

a third high-side transistor disposed on the fifth patterned metal layer;

a fourth high-side transistor disposed on the fifth patterned metal layer;

a second conductive clip electrically coupling the first high-side transistor with the first patterned metal layer;

a third conductive clip electrically coupling the second high-side transistor with the first patterned metal layer;

a fourth conductive clip electrically coupling the third high-side transistor with the third patterned metal layer; and

a fifth conductive clip electrically coupling the fourth high-side transistor with the third patterned metal layer.

16 . The half-bridge circuit power module of claim 15 , wherein:

the fourth patterned metal layer is electrically coupled with a first DC+ terminal via a first conductive post; and

the fifth patterned metal layer is electrically coupled with a second DC+ terminal via a second conductive post.

17 . A half-bridge circuit power module comprising:

a substrate including:

a first patterned metal layer disposed on a surface of the substrate and electrically coupled with an output terminal;

a second patterned metal layer disposed on the surface of the substrate and electrically coupled with a DC− terminal;

a third patterned metal layer disposed on the surface of the substrate and electrically coupled with the output terminal;

a first low-side transistor disposed on the first patterned metal layer;

a second low-side transistor disposed on the first patterned metal layer;

a third low-side transistor disposed on the first patterned metal layer;

a fourth low-side transistor disposed on the third patterned metal layer;

a fifth low-side transistor disposed on the third patterned metal layer;

a sixth low-side transistor disposed on the third patterned metal layer;

a first conductive clip electrically coupling the first low-side transistor and the fourth low-side transistor to the second patterned metal layer;

a second conductive clip electrically coupling the second low-side transistor and the fifth low-side transistor to the second patterned metal layer; and

a third conductive clip electrically coupling the third low-side transistor and the sixth low-side transistor to the second patterned metal layer.

18 . The half-bridge circuit power module of claim 17 , wherein the second patterned metal layer is electrically coupled with a DC− terminal.

19 . The half-bridge circuit power module of claim 18 , wherein the DC− terminal is electrically coupled with the second patterned metal layer via:

a first conductive post disposed on the second patterned metal layer between the first conductive clip and the second conductive clip, the second conductive clip being closer to the DC− terminal than the first conductive clip; and

a second conductive post disposed on the second patterned metal layer between third second conductive clip and the third conductive clip, the third conductive clip being closer to the DC− terminal than the second conductive clip.

20 . The half-bridge circuit power module of claim 19 , wherein a surface of the second conductive post coupled with the second patterned metal layer has an area that is smaller than an area of a surface of the first conductive post coupled with the second patterned metal layer.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 064502, FRAME 0293 Recorded Nov 14, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065566/0488 →
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
SECURITY INTEREST Recorded May 9, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 065402/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2023
From: JEON, OSEOB; IM, SEUNGWON; THIRUKOLURI, RAJANI KUMAR; PAUL, ROVEENDRA
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 062448/0646 →