IP Library Granted Patent US 12,287,708
Granted Patent B2
US 12,287,708 · App. 18/362,197 · Granted Apr 29, 2025

Automatic XOR data programming by memory die for uncorrectable page failure recovery

Inventors: Anantharaj Thalaimalai Vanaraj (San Jose, CA); Sai Gautham Thoppa (San Jose, CA); Dharmaraju Marenahally Krishna (Karnataka, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F11/1451G06F11/1435G06F11/1458
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Quick Facts
Patent No.
US 12,287,708
App. No.
18/362,197
Granted
Apr 29, 2025
Kind
B2
Abstract

Embodiments of the present technology provide non-volatile memory devices comprising memory dies that natively generate “exclusive OR (XOR) data pages” that can be used to recover data pages corrupted by UECC errors. Through memory die native-XOR data page generation, embodiments can recover data pages corrupted by UECC errors more efficiently, more rapidly, and with fewer resources than potential alternative technologies.

Claims (92)

1. A memory die comprising:

a controller operative to:

generate an exclusive OR (XOR) data page by performing an XOR operation between a first raw data page and a second raw data page,

generate a fixed content data page,

store the XOR data page on a first back-up data plane-data latch, and

store the fixed content data page on a second back-up data plane-data latch;

a raw data plane comprising:

a first raw data plane-data latch that stores the first raw data page, and

a second raw data plane-data latch that stores the second raw data page; and

a back-up data plane comprising:

the first back-up data plane-data latch that stores the XOR data page, and

the second back-up data plane-data latch that stores the fixed content data page.

2. The memory die of claim 1 , wherein generating the XOR data page is responsive to receiving an XOR enable signal.

3. The memory die of claim 1 , wherein:

the first raw data plane-data latch comprises a first lower page data latch;

the second raw data plane-data latch comprises a first middle page data latch;

the first back-up data plane-data latch comprises a second lower page data latch; and

the second back-up data plane-data latch comprises a second middle page data latch.

4. The memory die of claim 1 , wherein:

the controller is further operative to:

generate a second XOR data page data page by performing an XOR operation between a third raw data page and a fourth raw data page,

generate a second fixed content data page,

store the second XOR data page on a third back-up data plane-data latch, and

store the second fixed content data page on a fourth back-up data plane-data latch;

the raw data plane further comprises:

a third raw data plane-data latch that stores the third raw data page, and

a fourth raw data plane-data latch that stores the fourth raw data page; and

the back-up data plane further comprises:

the third back-up data plane-data latch that stores the second XOR data page, and

the fourth back-up data plane-data latch that stores the second fixed content data page.

5. The memory die of claim 1 , wherein values of the fixed content data page comprise all ones or all zeroes.

6. The memory die of claim 1 , wherein the controller is further operative to:

program the first and second raw data pages to a wordline of the raw data plane; and

program the XOR data page and the fixed content data page to a wordline of the back-up data plane.

7. The memory die of claim 6 , wherein the programming to the raw data plane and the back-up data plane is performed in parallel.

8. The memory die of claim 7 , wherein the controller is further operative to:

responsive to determining the first raw data page has become corrupted, recover the first raw data page by performing an XOR operation between the second raw data page and the XOR data page.

9. A memory device comprising:

a first memory die comprising:

a controller operative to:

generate a first exclusive OR (XOR) data page by performing an XOR operation between a first raw data page and a second raw data page,

generate a second XOR data page by performing an XOR operation between a third raw data page and a fourth raw data page,

generate a first fixed content data page and a second fixed content data page,

store the first XOR data page on a first back-up data plane-data latch,

store the first fixed content data page on a second back-up data plane-data latch,

store the second XOR data page on a third back-up data plane-data latch, and

store the second fixed content data page on a fourth back-up data plane-data latch;

a first back-up data plane comprising:

the first back-up data plane-data latch that stores the first XOR data page, and

the second back-up data plane-data latch that stores the first fixed content data page; and

a second back-up data plane comprising:

the third back-up data plane-data latch that stores the second XOR data page, and

the fourth back-up data plane-data latch that stores the second fixed content data page.

10. The memory device of claim 9 , further comprising:

a second memory die comprising:

a first raw data plane comprising:

a first raw data plane-data latch that stores the first raw data page, and

a second raw data plane-data latch that stores the second raw data page, and

a second raw data plane comprising:

a third raw data plane-data latch that stores the third raw data page, and

a fourth raw data plane-data latch that stores the fourth raw data page.

11. The memory device of claim 10 , wherein:

the first raw data plane-data latch comprises a first lower page data latch;

the second raw data plane-data latch comprises a first middle page data latch;

the third raw data plane-data latch comprises a second lower page data latch;

the fourth raw data plane-data latch comprises a second middle page data latch;

the first back-up data plane-data latch comprises a third lower page data latch; the second back-up data plane-data latch comprises a third middle page data latch;

the third back-up data plane-data latch comprises a fourth lower page data latch; and the fourth back-up data plane-data latch comprises a fourth middle page data latch.

12. The memory device of claim 9 , wherein values of the first and second fixed content data pages comprise all ones or all zeroes.

13. The memory device of claim 10 , wherein the second memory die further comprises a controller operative to:

program the first and second raw data pages to a wordline of the first raw data plane; and

program the third and fourth raw data pages to a wordline of the second raw data plane.

14. The memory device of claim 13 , wherein the controller of the first memory die is further operative to:

program the first XOR data page and the first fixed content data page to a wordline of the first back-up data plane; and program the second XOR data page and the second fixed content data page to a wordline of the second back-up data plane.

15. The memory device of claim 14 , wherein the controller of the second memory die is further operative to:

responsive to determining the first raw data page has become corrupted, recover the first raw data page by performing an XOR operation between the second raw data page and the first XOR data page.

16. A method performed by a controller on a memory die, the method comprising:

receiving an exclusive OR (XOR) enable signal;

responsive to receiving the XOR enable signal, generating an XOR data page by performing an XOR operation between a first raw data page and a second raw data page;

generating a fixed content data page;

storing the XOR data page on a first back-up data plane-data latch of the memory die; and

storing the fixed content data page on a second back-up data plane-data latch of the memory die.

17. The method of claim 16 , further comprising: responsive to determining the first raw data page has become corrupted, recover the first raw data page by performing an XOR operation between the second raw data page and the XOR data page.

18. The method of claim 16 , further comprising, in parallel:

programming the first and second raw data pages to a wordline of a raw data plane of the memory die; and

programming the XOR data page and the fixed content data page to a wordline of a back-up data plane of the memory die.

19. The method of claim 18 , further comprising:

responsive to receiving the XOR enable signal, generating a second XOR data page by performing an XOR operation between a third raw data page and a fourth raw data page;

generating a second fixed content data page;

storing the second XOR data page on a third back-up data plane-data latch of the memory die; and

storing the second fixed content data page on a fourth back-up data plane-data latch of the memory die.

20. The method of claim 19 , further comprising, in parallel: programming the third and fourth raw data pages to a wordline of the raw data plane; and programming the second XOR data page and the second fixed content data page to a wordline of the back-up data plane.

Assignments (5)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2025
From: THALAIMALAI VANARAJ, ANANTHARAJ; THOPPA, SAI GAUTHAM; MARENAHALLY KRISHNA, DHARMARAJU
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 070529/0322 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
Continuity (2)
Provisional Application 63509004 · Jun 19, 2023
Related Publication 20240419554A1 · Dec 19, 2024
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