Power saving during open block read with large block openness
A memory apparatus includes memory cells connected to word lines and operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is coupled to the word lines and is configured to program the memory cells in a program operation. Following programming of the memory cells connected to specific ones of the word lines, the control means is also configured to apply a predetermined dummy read voltage to the specific ones of the word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the word lines determined based on an amount of the memory cells that are programmed.
1 . A memory apparatus, comprising:
a plurality of blocks including memory cells that are disposed in memory holes and are each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states and being operable in one of a first read condition in which a word line voltage of the plurality of word lines is discharged and a second read condition in which the word line voltage of the plurality of word lines is coupled up to a residual voltage level; and
a control means coupled to the plurality of word lines and configured to:
program the memory cells in a program operation,
determine specific ones of the plurality of word lines of the plurality of blocks based on a quantity of the plurality of word lines connected to the memory cells of each of the plurality of blocks that are programmed;
following programming of the memory cells connected to the specific ones of the plurality of word lines, apply a predetermined dummy read voltage to the specific ones of the plurality of word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the plurality of word lines determined based on an amount of the memory cells that are programmed.
2 . The memory apparatus as set forth in claim 1 , wherein the control means is further configured to:
determine to which of a plurality of predetermined word line ranges each of the plurality of word lines being programmed belongs; and
identify one of the plurality of word lines being programmed as one of the specific ones of the plurality of word lines based on which of the plurality of predetermined word line ranges the one of the plurality of word lines being programmed belongs.
3 . The memory apparatus as set forth in claim 2 , further including a predetermined word line range parameter stored in the memory apparatus for each of the plurality of predetermined word line ranges, the predetermined word line range parameter indicates whether the dummy read operation should be performed, and the control means is further configured to determine whether the dummy read operation should be performed for the one of the plurality of word lines being programmed based on the predetermined word line range parameter.
4 . The memory apparatus as set forth in claim 1 , wherein the memory cells are programmed according to a predetermined order of the plurality of word lines and the control means is further configured to skip the dummy read operation for ones of the plurality of word lines connected to the memory cells being programmed later in the predetermined order.
5 . The memory apparatus as set forth in claim 1 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, and the control means is further configured to perform the dummy read operation based on a vertical height of each of the plurality of word lines in the stack.
6 . The memory apparatus as set forth in claim 5 , wherein the plurality of word lines includes a top word line adjacent the drain-side select gate transistor and a bottom word line adjacent the source-side select gate transistor, the memory cells connected to the bottom word line are programmed first and the memory cells connected to the top word line are programmed last and the control means is further configured to perform the dummy read operation for a first group of one of the plurality of word lines being relatively closer to and including the bottom word line and skip the dummy read operation for a second group of one of the plurality of word lines being relatively closer to and including the top word line.
7 . A controller in communication with a memory apparatus that has a plurality of blocks including memory cells that are disposed in memory holes and are each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states and being operable in one of a first read condition in which a word line voltage of the plurality of word lines is discharged and a second read condition in which the word line voltage of the plurality of word lines is coupled up to a residual voltage level, the controller configured to:
instruct the memory apparatus to program the memory cells in a program operation;
determine specific ones of the plurality of word lines based on a quantity of the plurality of word lines connected to the memory cells of each of the plurality of blocks that are programmed;
following programming of the memory cells connected to the specific ones of the plurality of word lines, instruct the memory apparatus to apply a predetermined dummy read voltage to the specific ones of the plurality of word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the plurality of word lines determined based on an amount of the memory cells that are programmed.
8 . The controller as set forth in claim 7 , wherein the controller is further configured to:
determine to which of a plurality of predetermined word line ranges each of the plurality of word lines being programmed belongs; and
identify one of the plurality of word lines being programmed as one of the specific ones of the plurality of word lines based on which of the plurality of predetermined word line ranges the one of the plurality of word lines being programmed belongs.
9 . The controller as set forth in claim 7 , wherein the memory cells are programmed according to a predetermined order of the plurality of word lines and the controller is further configured to instruct the memory apparatus to skip the dummy read operation for ones of the plurality of word lines connected to the memory cells being programmed later in the predetermined order.
10 . The controller as set forth in claim 7 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, and the controller is further configured to instruct the memory apparatus to perform the dummy read operation based on a vertical height of each of the plurality of word lines in the stack.
11 . The controller as set forth in claim 10 , wherein the plurality of word lines includes a top word line adjacent the drain-side select gate transistor and a bottom word line adjacent the source-side select gate transistor, the memory cells connected to the bottom word line are programmed first and the memory cells connected to the top word line are programmed last and the controller is further configured to instruct the memory apparatus to perform the dummy read operation for a first group of one of the plurality of word lines being relatively closer to and including the bottom word line and skip the dummy read operation for a second group of one of the plurality of word lines being relatively closer to and including the top word line.
12 . A method of operating a memory apparatus including a plurality of blocks with memory cells that are disposed in memory holes and are each connected to one of a plurality of word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states and being operable in one of a first read condition in which a word line voltage of the plurality of word lines is discharged and a second read condition in which the word line voltage of the plurality of word lines is coupled up to a residual voltage level, the method comprising the steps of:
programming the memory cells in a program operation;
determine specific ones of the plurality of word lines based on a quantity of the plurality of word lines connected to the memory cells of each of the plurality of blocks that are programmed; and
following programming of the memory cells connected to the specific ones of the plurality of word lines, applying a predetermined dummy read voltage to the specific ones of the plurality of word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the plurality of word lines determined based on an amount of the memory cells that are programmed.
13 . The method as set forth in claim 12 , further including the steps of:
determining to which of a plurality of predetermined word line ranges each of the plurality of word lines being programmed belongs; and
identifying one of the plurality of word lines being programmed as one of the specific ones of the plurality of word lines based on which of the plurality of predetermined word line ranges the one of the plurality of word lines being programmed belongs.
14 . The method as set forth in claim 13 , wherein the memory apparatus further includes a predetermined word line range parameter stored in the memory apparatus for each of the plurality of predetermined word line ranges, the predetermined word line range parameter indicates whether the dummy read operation should be performed, and the method further includes the step of determining whether the dummy read operation should be performed for the one of the plurality of word lines being programmed based on the predetermined word line range parameter.
15 . The method as set forth in claim 12 , wherein the memory cells are programmed according to a predetermined order of the plurality of word lines and the method further includes the step of skipping the dummy read operation for ones of the plurality of word lines connected to the memory cells being programmed later in the predetermined order.
16 . The method as set forth in claim 12 , wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes, the drain-side select gate transistor of each of the memory holes is connected to one of a plurality of bit lines and the source-side select gate transistor of each of the memory holes is connected to a source line, and the method further includes the step of performing the dummy read operation based on a vertical height of each of the plurality of word lines in the stack.
17 . The method as set forth in claim 16 , wherein the plurality of word lines includes a top word line adjacent the drain-side select gate transistor and a bottom word line adjacent the source-side select gate transistor, the memory cells connected to the bottom word line are programmed first and the memory cells connected to the top word line are programmed last and the method further includes the step of performing the dummy read operation for a first group of one of the plurality of word lines being relatively closer to and including the bottom word line and skip the dummy read operation for a second group of one of the plurality of word lines being relatively closer to and including the top word line.