READ METHOD ENHANCEMENT TO REDUCE READ DISTURB IN MIXED-MODE MEMORY STORAGE REGIONS

1 . A non-volatile storage system, comprising:

a non-volatile memory including a plurality of blocks of non-volatile storage elements; and

control circuitry in communication with the non-volatile memory, the control circuitry configured to:

perform a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of the plurality of blocks;

perform the first memory operation, using the device parameter information associated with the first storage region type;

perform a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and

perform the second memory operation, using the device parameter information associated with the second storage region type.

2 . The non-volatile storage system of claim 1 , wherein the first storage region type is of a Quad-Level Cell storage type.

3 . The non-volatile storage system of claim 1 , wherein the second storage region type is of a Triple-Level Cell storage type.

4 . The non-volatile storage system of claim 1 , wherein performing the first read operation includes accessing a first wordline of the first block to access the device parameter information associated with the first storage region type.

5 . The non-volatile storage system of claim 1 , wherein performing the second read operation includes accessing a second wordline of the second block to access the device parameter information associated with the second storage region type.

6 . The non-volatile storage system of claim 1 , wherein unselected wordlines of the first block have an erase-state.

7 . The non-volatile storage system of claim 1 , wherein unselected wordlines of the second block have an erase-state.

8 . The non-volatile storage system of claim 4 , wherein performing the first read operation further includes applying a voltage of zero volts to the first wordline and unselected wordlines of the first block.

9 . The non-volatile storage system of claim 5 , wherein performing the second read operation further includes applying a voltage of zero volts to the second wordline and unselected wordlines of the second block.

10 . A method of operating a non-volatile semiconductor memory device, the method comprising:

performing a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of a plurality of blocks;

performing the first memory operation, using the device parameter information associated with the first storage region type;

performing a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and

performing the second memory operation, using the device parameter information associated with the second storage region type.

11 . The method of claim 10 , wherein the first storage region type is of a Quad-Level Cell storage type.

12 . The method of claim 10 , wherein the second storage region type is of a Triple-Level Cell storage type.

13 . The method of claim 10 , wherein performing the first read operation includes accessing a first wordline of the first block to access the device parameter information associated with the first storage region type.

14 . The method of claim 10 , wherein performing the second read operation includes accessing a second wordline of the second block to access the device parameter information associated with the second storage region type.

15 . The method of claim 10 , wherein performing the first read operation further includes applying a voltage of zero volts to a first wordline and unselected wordlines of the first block.

16 . The method of claim 10 , wherein performing the second read operation further includes applying a voltage of zero volts to a second wordline and unselected wordlines of the second block.

17 . An apparatus, comprising:

a means for performing a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of a plurality of blocks;

a means for performing the first memory operation, using the device parameter information associated with the first storage region type;

a means for performing a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and

a means for performing the second memory operation, using the device parameter information associated with the second storage region type.

18 . The apparatus of claim 17 , wherein the first storage region type is of a Quad-Level Cell storage type.

19 . The apparatus of claim 17 , wherein the second storage region type is of a Triple-Level Cell storage type.

20 . The apparatus of claim 17 , wherein performing the first read operation includes accessing a first wordline of the first block to access the device parameter information associated with the first storage region type and performing the second read operation includes accessing a second wordline of the second block to access the device parameter information associated with the second storage region type.