Host bandwidth limited SSDs with high-rate NANDs
When the overall NAND bandwidth exceeds the bandwidth of a host device, back pressure builds and the full potential of the NAND is not utilized. This back pressure may be relieved by NAND arbitration, where a device controller selects and interleaves different sets of NANDs over the course of subsequent states. The number of NANDs that participate in this arbitration depends on the host speed to NAND speed ratio. At each state, different sets of NAND are selected by exchanging NANDs that were used in a previous state with NANDS that were not used in a previous state in an interleaving manner. At each state, a pre-determined amount of data will be sent to the selected set of NAND. Once the device determines that all the NANDs participating in the arbitration are ready to be programmed, the device will program the NANDs.
1 . A data storage device, comprising:
a memory device comprising a plurality of memory elements; and
a controller coupled to the memory device, wherein the controller is configured to:
determine that a plurality of memory elements will participate in a host limited memory device arbitration scheme, wherein the arbitration scheme comprises a transition state and a steady state, wherein the transition state comprises several time slots where the plurality of memory elements start to fill a pipeline, wherein a first time slot of the transition state comprises sending data at full host bandwidth to a memory element of the plurality of memory elements, wherein a second time slot of the transition state which is after the first time slot comprises sending data at half of the full host bandwidth to a memory element of the plurality of memory elements, and wherein a third time slot of the transition state which is after the second time slot comprises sending data at a third of the full host bandwidth to a memory element of the plurality of elements;
determine a first host speed to memory element speed ratio;
select a first set of memory elements of the plurality of memory elements at a first state based on the first host speed to memory element speed ratio;
determine a second host speed to memory element speed ratio; and
select a second set of memory elements of the plurality of memory elements at a second state based on the second host speed to memory element speed ratio, wherein the second set of memory elements is different from the first set of memory elements.
2 . The data storage device of claim 1 , wherein the memory elements are NAND.
3 . The data storage device of claim 1 , wherein the second set of memory elements interleaves the first set of memory elements.
4 . The data storage device of claim 3 , wherein the interleaving of the first set of memory elements is cyclical.
5 . The data storage device of claim 1 , wherein the controller is further configured to select sets of memory elements at subsequent states based on corresponding host speed to memory element speed ratio at the subsequent states.
6 . The data storage device of claim 1 , wherein a first memory element is in the first set of memory elements and the second set of memory elements.
7 . The data storage device of claim 1 , wherein the controller is further configured to:
select a base memory element from the first set of memory elements at the first state, wherein the base memory element is a first memory element that will participate in arbitration; and
update the base memory element, wherein the updated base memory element points to a unused memory element of the plurality of memory elements.
8 . The data storage device of claim 1 , wherein the first and second host speed to memory element speed ratios are different.
9 . The data storage device of claim 1 , wherein the controller is further configured to:
calculate a number of active memory elements, wherein the number of active memory elements is a number of memory elements equal to the total number or memory elements.
10 . The data storage device of claim 1 , wherein the controller is further configured to:
send data to the first set of memory elements at a pre-determined interval;
select the second set of memory elements at the second state, the second set of memory elements comprising at least one memory element not included in the first set of memory elements;
send data to the second set of memory elements at the pre-determined interval;
determine whether the plurality of memory elements that participated in arbitration are ready to be programed; and
program the memory elements.
11 . A data storage device, comprising:
a memory device comprising a plurality of memory elements; and
a controller coupled to the memory device, wherein the controller is configured to:
determine at least one memory element of the plurality of memory elements that will participate in determine that a plurality of memory elements will participate in a host limited memory device arbitration scheme, wherein the arbitration scheme comprises a transition state and a steady state, wherein the transition state comprises several time slots where the plurality of memory elements start to fill a pipeline, wherein a first time slot of the transition state comprises sending data at full host bandwidth to a memory element of the plurality of memory elements, wherein a second time slot of the transition state which is after the first time slot comprises sending data at half of the full host bandwidth to a memory element of the plurality of memory elements, and wherein a third time slot of the transition state which is after the second time slot comprises sending data at a third of the full host bandwidth to a memory element of the plurality of elements;
calculate a host speed to memory element speed ratio;
calculate a number of active memory elements;
select a first set of memory elements of the plurality of memory elements at a first state from the at least one memory element that will participate in arbitration, wherein the number of memory elements in the first set is equal to the number of active memory elements;
send data to the first set of memory elements;
program the first set of memory elements; and
select a second set of memory elements at a second state.
12 . The data storage device of claim 11 , wherein the second set of memory elements comprises at least one memory element not included in the first set of memory elements.
13 . The data storage device of claim 11 , wherein the controller is further configured to select the second set of memory elements by exchanging at least one memory element used in the first set of memory elements for at least one unused memory element from the memory elements that will participate in arbitration.
14 . The data storage device of claim 11 , wherein the number of active memory elements is less than the number of memory elements that will participate in arbitration.
15 . The data storage device of claim 11 , wherein the controller is further configured to send data to the second set of memory elements and then program the second set of memory elements.
16 . The data storage device of claim 11 , wherein the number of active memory elements for the second set of memory element at the second state is a number of memory elements equal to:
the plurality of memory elements.
17 . The data storage device of claim 11 , wherein the controller is further configured to:
determine a base memory element at a first state, wherein the base memory element is a first memory element that will participate in arbitration; and
update the base memory element, wherein the updated base memory element points to a first unused memory element of the plurality of memory elements.
18 . A data storage device, comprising:
means to store data; and
a controller coupled to the means to store data, wherein the controller is configured to:
determine a plurality of memory elements of the means to store data that will participate in a host limited memory device arbitration scheme, wherein the arbitration scheme comprises a transition state and a steady state, wherein the transition state comprises several time slots where the plurality of memory elements start to fill a pipeline, wherein a first time slot of the transition state comprises sending data at full host bandwidth to a memory element of the plurality of memory elements, wherein a second time slot of the transition state which is after the first time slot comprises sending data at half of the full host bandwidth to a memory element of the plurality of memory elements, and wherein a third time slot of the transition state which is after the second time slot comprises sending data at a third of the full host bandwidth to a memory element of the plurality of elements;
select a first set of memory elements at a first state from the plurality of memory elements that will participate in arbitration;
send data to the first set of memory elements at a pre-determined interval;
select a second set of memory elements at a second state from the plurality of memory elements, the second set of memory elements comprising at least one memory element not included in the first set of memory elements;
send data to the second set of memory elements at the pre-determined interval;
determine whether the plurality of memory elements that participated in arbitration are ready to be programed; and
program the plurality of memory elements that participated in arbitration.
19 . The data storage device of claim 18 , wherein a memory element is ready to be programmed after a predetermined amount of data is received by the memory element.
20 . The data storage device of claim 18 , wherein the pre-determined interval is 4 KB.