LATERAL SUB-BLOCK MODE IN A MEMORY DEVICE
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines and that are divided into at least two laterally divided sub-blocks. Control circuitry programs the memory cells of one of the sub-blocks in a plurality of program loops. During at least one of the program loops, the control circuitry ramps down a selected word line being programmed from a reference voltage. After beginning to ramp down the selected word line from the reference voltage, the control circuitry sequentially ramps down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block. Then, the control circuitry ramps up a plurality of unselected word lines that are distant from the selected word line. Next, the control circuitry ramps up the selected word line to a programming voltage.
1 . A method of performing a programming operation in a memory device, comprising the steps of:
preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines;
with the memory block operating in a lateral sub-block mode;
ramping down a selected word line being programmed from a reference voltage;
after beginning to ramp down the selected word line from the reference voltage, sequentially ramping down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block;
after the unselected word lines have been sequentially ramped down, ramping up a plurality of unselected word lines that are distant from the selected word line; and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramping up the selected word line to a programming voltage.
2 . The method as set forth in claim 1 , wherein the step of sequentially ramping down the plurality of unselected word lines begins with only ramping down at least two word lines that are nearest the selected word line and then only ramping down at least two next closest word lines and continues until all of the unselected word lines in the memory block have begun to ramp down from the pass voltages.
3 . The method as set forth in claim 2 , wherein the step of sequentially ramping down the plurality of unselected word lines includes a first stage and a second stage,
wherein during the first stage, a first number of unselected word lines simultaneously begin to ramp down,
wherein during the second stage, a second number of unselected word lines simultaneously begin to ramp down, and
wherein the second number of unselected word lines is greater than the first number of unselected word lines.
4 . The method as set forth in claim 3 , wherein the first number of unselected word lines includes no more than four unselected word lines.
5 . The method as set forth in claim 1 , wherein the step of ramping down the selected word line from the reference voltage includes ramping the selected word line down to a negative voltage.
6 . The method as set forth in claim 5 , wherein the step of sequentially ramping down the plurality of unselected word lines from the pass voltages includes ramping the unselected word lines down to approximately zero Volts.
7 . The method as set forth in claim 5 , wherein after the step of ramping up the plurality of unselected word lines that are distant from the selected word line and prior to the step of ramping up the selected word line to the programming voltage, the method further includes the step of ramping up the selected word line from the negative voltage to a positive voltage that is less than the programming voltage.
8 . The method as set forth in claim 1 , wherein after the step of ramping up the selected word line to the programming voltage, the method further includes the step of ramping up a plurality of remaining unselected word lines to pass voltages.
9 . A memory device for performing a programming operation, comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the array being divided into at least two laterally divided sub-blocks;
control circuitry that is configured to program the memory cells of one of the sub-blocks in a plurality of program loops, during at least one of the program loops the control circuitry being configured to;
ramp down a selected word line being programmed from a reference voltage;
after beginning to ramp down the selected word line from the reference voltage, sequentially ramp down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block;
after the unselected word lines have been sequentially ramped down, ramp up a plurality of unselected word lines that are distant from the selected word line; and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramp up the selected word line to a programming voltage.
10 . The memory device as set forth in claim 9 , wherein when sequentially ramping down the plurality of unselected word lines, the control circuitry is configured to initially only ramp down at least two word lines that are nearest the selected word line and then only ramp down at least two next closest word lines and continue to ramp down the unselected word lines until all of the unselected word lines in the memory block have begun to ramp down from the pass voltages.
11 . The memory device as set forth in claim 10 , wherein the control circuitry is configured to sequentially ramp down the plurality of unselected word lines in a first stage and a second stage,
wherein during the first stage, the control circuitry simultaneously begins to ramp down a first number of unselected word lines,
wherein during the second stage, the control circuitry simultaneously begins to ramp down a second number of unselected word lines, and
wherein the second number of unselected word lines is greater than the first number of unselected word lines.
12 . The memory device as set forth in claim 11 , wherein the first number of unselected word lines includes no more than four unselected word lines.
13 . The memory device as set forth in claim 9 , wherein the control circuitry is configured to ramp down the selected word line from the reference voltage to a negative voltage.
14 . The memory device as set forth in claim 13 , wherein the circuitry is configured to sequentially ramp down the plurality of unselected word lines from the pass voltages to approximately zero Volts.
15 . The memory device as set forth in claim 13 , wherein after ramping up the plurality of unselected word lines that are distant from the selected word line and prior to ramping up the selected word line to the programming voltage, the control circuitry is further configured to ramp up the selected word line from the negative voltage to a positive voltage that is less than the programming voltage.
16 . The memory device as set forth in claim 9 , wherein after ramping up the selected word line to the programming voltage, the control circuitry is further configured to ramp up a plurality of remaining unselected word lines to pass voltages.
17 . An apparatus for performing a programming operation in a memory device, comprising:
a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the array being divided into at least two laterally divided sub-blocks;
a programming means for programming the memory cells of one of the sub-blocks in a plurality of program loops, during at least one of the program loops the programming means being configured to;
ramp down a selected word line being programmed from a reference voltage,
after beginning to ramp down the selected word line from the reference voltage, sequentially ramp down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block,
after the unselected word lines have been sequentially ramped down, ramp up a plurality of unselected word lines that are distant from the selected word line, and
after the unselected word lines that are distant from the selected word line have begun to ramp up, ramp up the selected word line to a programming voltage.
18 . The apparatus as set forth in claim 17 , wherein when sequentially ramping down the plurality of unselected word lines, the programming means is configured to initially only ramp down at least two word lines that are nearest the selected word line and then only ramp down at least two next closest word lines and continue to ramp down the unselected word lines until all of the unselected word lines in the memory block have begun to ramp down from the pass voltages.
19 . The apparatus as set forth in claim 18 , wherein the programming means is configured to sequentially ramp down the plurality of unselected word lines in a first stage and a second stage,
wherein during the first stage, the programming means simultaneously begins to ramp down a first number of unselected word lines,
wherein during the second stage, the programming means simultaneously begins to ramp down a second number of unselected word lines, and
wherein the second number of unselected word lines is greater than the first number of unselected word lines.
20 . The apparatus as set forth in claim 19 , wherein the first number of unselected word lines includes no more than four unselected word lines.