SSD WAFER DEVICE AND METHOD OF MANUFACTURING SAME
A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.
1 . A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, and a plurality of memory dies, each memory die of the plurality of memory dies comprising a plurality of bond pads at the first major surface; and
a second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the fourth major surface, at a second end of the electrical interconnect opposite the first end, the second terminal of each of the electrical interconnects configured to transfer signals between the second semiconductor wafer and an external device;
wherein the first major surface of the first semiconductor wafer is coupled to the third major surface of the second semiconductor wafer, with the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads.
2 . The SSD wafer device of claim 1 , wherein the second terminals of the plurality of electrical interconnects cluster together in a rectangular grid pattern at a center of the fourth major surface of the second semiconductor wafer.
3 . The SSD wafer device of claim 2 , further comprising one or more SSD controllers electrically coupled to the second terminals of the plurality of electrical interconnects.
4 . The SSD wafer device of claim 3 , wherein the at least one SSD controller is flip-chip bonded to the second terminal of at least some of the plurality of electrical interconnects.
5 . The SSD wafer device of claim 1 , wherein the second terminals of the plurality of electrical interconnects are clustered together in a plurality of groups at the fourth major surface of the second semiconductor wafer.
6 . The SSD wafer device of claim 5 , further comprising one or more SSD controllers electrically coupled to the second terminals of the plurality of electrical interconnects.
7 . The SSD wafer device of claim 5 , further comprising:
a plurality of signal/data connectors directly coupled to the second terminals of the plurality of electrical interconnects; and
an SSD controller coupled to the plurality of signal/data connectors to transfer one or both of signals and data to and from the second terminals of the plurality of electrical interconnects.
8 . The SSD wafer device of claim 7 , wherein the SSD controller comprises a master SSD controller, and the plurality of signal/data connectors comprise SSD controllers coupled to the master SSD controller.
9 . The SSD wafer device of claim 1 , wherein the first and second semiconductor wafers include matching circular footprints.
10 . The SSD wafer device of claim 1 , wherein the second ends of the electrical interconnects are exposed at the fourth major surface upon thinning of the second semiconductor wafer.
11 . The SSD wafer device of claim 1 , further comprising pads formed at the first and second ends of each of the electrical interconnects.
12 . A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, and a plurality of memory dies, each memory die comprising a plurality of bond pads at the first major surface;
a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the fourth major surface, at a second end of the electrical interconnect opposite the first end, the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads; and
one or more SSD controllers electrically coupled to the second terminals of the plurality of electrical interconnects.
13 . The SSD wafer device of claim 12 , wherein at least one SSD controller of the one or more SSD controllers comprises bond pads that are directly coupled to the second terminals of the plurality of electrical interconnects.
14 . The SSD wafer device of claim 12 , wherein the second terminals of the plurality of interconnects are grouped together in a single cluster, the one or more SSD controllers comprising a single controller mounted to the fourth major surface of the second semiconductor wafer on top of the cluster of second terminals.
15 . The SSD wafer device of claim 14 , wherein the single controller is flip-chip bonded to the second terminal of at least some of the plurality of electrical interconnects.
16 . The SSD wafer device of claim 12 , wherein the second terminals of the plurality of electrical interconnects are clustered together in a plurality of groups at the fourth major surface of the second semiconductor wafer.
17 . The SSD wafer device of claim 16 , further comprising:
a plurality of signal/data connectors directly coupled to the second terminals of the plurality of electrical interconnects in the plurality of groups 1 ; and
wherein the one or more controllers comprise an SSD controller coupled to the plurality of signal/data connectors to transfer one or both of signals and data to and from the second terminals of the plurality of electrical interconnects.
18 . The SSD wafer device of claim 17 , wherein the SSD controller comprises a master SSD controller, and the plurality of signal/data connectors comprise SSD controllers coupled to the master SSD controller.
19 . The SSD wafer device of claim 12 , wherein the second ends of the electrical interconnects are exposed at the fourth major surface upon thinning of the second semiconductor wafer.
20 . A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, and a plurality of NAND dies, each NAND die of the plurality of NAND dies comprising a plurality of bond pads at the first major surface;
a second semiconductor wafer coupled to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and electrical interconnect means comprising a first end at the third major surface and a second end at the fourth major surface;
wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads.