IP Library Granted Patent US 12,592,264
Granted Patent Utility
US 12,592,264 · Confirmation No. 6590

REDUCTION IN CHIP AREA THROUGH DESIGN-TECHNOLOGY CO-OPTIMIZATION

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Quick Facts
Patent No.
US 12,592,264
App. No.
18/758,643
Filed
2024-06-28
Granted
2026-03-31
Pub. No.
US20260004822A1
Examiner
LUU, PHO M
Art Unit
2824
PTA
0 days