Embedded PHY (EPHY) IP Core for FPGA
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.
1 . A testing device, comprising:
a field programmable gate array (FPGA);
means to increase amplitude of a signal received from a device under testing (DUT) of a first speed to an amplitude of a signal of a second speed, wherein the means to increase is coupled to the FPGA; and
means to decrease amplitude of a signal received from a DUT of the second speed to an amplitude of a signal of the first speed, wherein the means to decrease is coupled to the FPGA.
2 . The testing device of claim 1 , further comprising means to detect entering into and exiting from hibernation states.
3 . The testing device of claim 1 , wherein the means to increase and the means to decrease are distinct.
4 . The testing device of claim 1 , further comprising means for sending multiple transmissions from the testing device to a DUT.
5 . The testing device of claim 4 , wherein a transmission speed of at least one transmission of the multiple transmissions is different than a transmission speed of another transmission of the multiple transmissions.
6 . The testing device of claim 1 , wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed.
7 . A testing device, comprising:
a field programmable gate array (FPGA); and
an embedded physical layer (EPHY), the EPHY including:
a logic portion comprising a low speed interface and a high speed interface, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the low speed interface and the high speed interface; and
a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
a first differential amplifier configured to increase amplitude of a signal received from a device under testing (DUT) of a first speed to an amplitude of a signal of a second speed, wherein the first differential amplifier is coupled to the FPGA; and
a second differential amplifier configured to decrease amplitude of a signal received from a DUT of the second speed to an amplitude of a signal of the first speed, wherein the second differential amplifier is coupled to the FPGA.
8 . The testing device of claim 7 , further comprising:
a plurality of transmission multiplexers (MUXs); and
a plurality of receiving MUXs.
9 . The testing device of claim 8 , wherein:
the low speed interface is coupled to a first transmission MUX of the plurality of transmission MUXs;
the low speed interface is coupled to a first receiving MUX of the plurality of receiving MUXs;
the high speed interface is coupled to a second transmission MUX of the plurality of transmission MUXs; and
the high speed interface is coupled to a second receiving MUX of the plurality of receiving MUXs.
10 . The testing device of claim 7 , further comprising means for sending multiple transmissions from the testing device to a DUT, wherein a transmission speed of at least one transmission of the multiple transmissions is different than a transmission speed of another transmission of the multiple transmissions.
11 . The testing device of claim 7 , wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed.
12 . The testing device of claim 7 , wherein the glue hardware further comprises:
an impedance detection unit coupled to the FPGA; and
a phase lock loop (PLL) coupled to the FPGA.
13 . The testing device of claim 7 , further comprising one or more storage units coupled to the FPGA.
14 . A testing device, comprising:
a field programmable gate array (FPGA); and
an embedded physical layer (EPHY), the EPHY including:
a logic portion having a first logical phy and a second logical phy, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the first and second logical phys; and
a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
a first differential amplifier configured to increase amplitude of a signal received from a device under testing (DUT) of a first speed to an amplitude of a signal of a second speed, wherein the first differential amplifier is coupled to the FPGA;
a first multiplexer (MUX) coupled to the first differential amplifier;
a second differential amplifier configured to decrease amplitude of a signal received from a DUT of the second speed to an amplitude of a signal of the first speed, wherein the second differential amplifier is coupled to the FPGA; and
a second MUX coupled to the second differential amplifier.
15 . The testing device of claim 14 , wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed.
16 . The testing device of claim 14 , wherein the first MUX and the first differential amplifier are coupled to the FPGA using a first transmission line, wherein the second MUX and the second differential amplifier are coupled to the FPGA using a second transmission line.
17 . The testing device of claim 14 , wherein the glue hardware further comprises an impedance detection unit coupled to the FPGA.
18 . The testing device of claim 17 , wherein the impedance detection unit comprises an adjustable regulator and one or more comparators.
19 . The testing device of claim 14 , further comprising:
means to detect entering into and exiting from hibernation states; and
one or more storage units coupled to the FPGA.
20 . The testing device of claim 14 , further comprising means for sending multiple transmissions from the testing device to a DUT, wherein a transmission speed of at least one transmission of the multiple transmissions is different than a transmission speed of another transmission of the multiple transmissions.