LINK RECEIVER CIRCUITRY FOR CONTROLLER-MEMORY DEVICE INTERFACES IN DATA STORAGE DEVICES
A receiver circuitry in a storage device may operate in stages. An amplifier in a first stage may receive an input and produce a high gain for all speeds with gain booster cells and a complementary input folded cascade structure. An equalizer including a resistor and a capacitor may increase the gain at high speeds in a second stage. In a third stage, a level down shifter may correct a duty cycle error resulting from shifting a signal across domain. The receiver circuitry may thus be used in different categories of storage devices with varying requirements.
1 . A receiver circuitry in a storage device to provide an interface between a controller and a memory device in the storage device, the receiver circuitry comprises:
an amplifier to receive an input and produce a high gain at high and low speeds;
an equalizer to increase gain at high speeds; and
a skew balanced level down shifter to correct a duty cycle error resulting from shifting a signal across domains.
2 . The receiver circuitry of claim 1 , wherein the amplifier is a complimentary amplifier that receives an input of approximately 200 milli-Volts and produces the high gain in a first stage.
3 . The receiver circuitry of claim 1 , wherein the amplifier boosts the gain at all speeds with a complementary input folded cascade structure.
4 . The receiver circuitry of claim 1 , wherein complementary inputs into the amplifier provide a high input common mode range.
5 . The receiver circuitry of claim 1 , wherein the amplifier includes gain booster cells and devices to provide additional gain and a large output swing within an operating range.
6 . The receiver circuitry of claim 1 , wherein the equalizer includes one resistor and one capacitor.
7 . The receiver circuitry of claim 6 , wherein peak frequency in the equalizer is tunable through the capacitor.
8 . The receiver circuitry of claim 6 , wherein the equalizer provides a low impedance path through the resistor to improve a bandwidth of a first stage.
9 . The receiver circuitry of claim 1 , wherein the skew balanced level down shifter receives two signals with delay between the signals from the equalizer, wherein a first signal is an inverted signal of a second signal.
10 . The receiver circuitry of claim 1 , wherein the skew balanced level down shifter balances a skew, negates an impact of the skew, and level down shifts the signal to a core voltage.
11 . The receiver circuitry of claim 1 , wherein the skew balanced level down shifter comprises a differential level down shifter with a skew balancer and duty cycle balancers.
12 . A receiver circuitry in a storage device to provide an interface between a controller and a memory device in the storage device, the receiver circuitry comprises:
an amplifier to operate in a first stage, receive an input. and produce a high gain with a complementary input folded cascade structure;
an equalizer to operate in a second stage, wherein the equalizer includes a resistor and a capacitor, and the equalizer increases the gain at high speeds; and
a level down shifter to operate in a third stage to correct a duty cycle error resulting from shifting a signal across domains.
13 . The receiver circuitry of claim 12 , wherein the first stage includes gain booster cells and additional devices to provide additional gain.
14 . The receiver circuitry of claim 12 , wherein the second stage provides a low impedance path through the resistor to improve the bandwidth of the first stage.
15 . A method for interfacing between a controller and a memory device in a storage device using a receiver circuitry in the storage device, the method comprising:
receiving an input and producing a high gain with gain booster cells and a complementary input folded cascade structure in a first stage;
increasing the gain at high speeds with an equalizer in a second stage; and
correcting a duty cycle error resulting from shifting a signal across domain with a level down shifter in a third stage.