Apparatus and methods for detecting coupling faults in non-volatile memory devices
An apparatus is provided that includes a memory die including non-volatile memory cells coupled to a signal line, a switching circuit including a control terminal coupled to a first conductor, the switching circuit configured to selectively couple the signal line to a power supply based on a signal level on the first conductor, a second conductor capacitively coupled to the first conductor, and a control circuit coupled to the switching circuit. The control circuit is configured to detect a defect in the first conductor by coupling the second conductor to a first voltage source, coupling the signal line to a second voltage source, and detecting a drop in a voltage of the second voltage source.
1 . An apparatus comprising:
a memory die comprising non-volatile memory cells coupled to a signal line;
a switching circuit comprising a control terminal coupled to a first conductor, the switching circuit configured to selectively couple the signal line to a power supply based on a signal level on the first conductor;
a second conductor capacitively coupled to the first conductor; and
a control circuit coupled to the switching circuit, the control circuit configured to detect a defect in the first conductor by:
coupling the second conductor to a first voltage source;
coupling the signal line to a second voltage source; and
detecting a drop in a voltage of the second voltage source.
2 . The apparatus of claim 1 , wherein:
the non-volatile memory cells are coupled to a source line; and
the signal line is coupled to the source line.
3 . The apparatus of claim 1 , wherein the first conductor is coupled to a transistor control terminal.
4 . The apparatus of claim 1 , wherein the first voltage source comprises an erase voltage.
5 . The apparatus of claim 1 , wherein the memory die and/or the control circuit comprises the second voltage source.
6 . The apparatus of claim 1 , wherein the first conductor comprises a partial or complete opening.
7 . The apparatus of claim 1 , wherein the first conductor comprises a first portion and a second portion, wherein an opening separates the first portion and the second portion.
8 . The apparatus of claim 1 , wherein:
the first conductor comprises a first portion coupled to a voltage source, and a second portion that is coupled to the control terminal of the switching circuit; and
the second portion is partially or fully separated from the first portion.
9 . The apparatus of claim 1 , wherein the second conductor comprises a bit line.
10 . The apparatus of claim 1 , wherein the first conductor is disposed adjacent the second terminal.
11 . The apparatus of claim 1 , wherein the power supply comprises GROUND.
12 . The apparatus of claim 1 , wherein the switching circuit is further configured to selectively discharge the signal line to GROUND based on a signal level on the first conductor.
13 . A method comprising:
providing a memory system comprising a memory die and a discharge circuit, the memory die comprising a non-volatile memory cell coupled to a bit line and a source line, the discharge circuit configured to selectively discharge a signal line to GROUND based on a signal level of a control signal line, the signal line coupled to the source line;
detecting a leakage current in a power supply coupled to the discharge circuit;
coupling the bit line to a first voltage source;
coupling the signal line to a second voltage source; and
detecting a drop in a voltage of the second voltage source,
wherein the drop in the voltage of the second voltage source increases as a voltage of the first voltage source increases.
14 . The method of claim 13 , wherein the control signal line comprises a partial or complete opening.
15 . The method of claim 13 , wherein the control signal line comprises a first portion and a second portion, wherein an opening separates the first portion and the second portion.
16 . The method of claim 13 , wherein the bit line is capacitively coupled to the control signal line.
17 . The method of claim 13 , wherein the first voltage source comprises any of a program voltage and an erase voltage.
18 . The method of claim 13 , wherein the memory die comprises the second voltage source.
19 . The method of claim 13 , wherein the second voltage source is internally generated in the memory die.
20 . A memory system comprising:
a NAND string comprising non-volatile memory cells coupled to a signal line;
a switching circuit comprising a transistor comprising a gate terminal coupled to a first conductor, the switching circuit configured to selectively discharge the signal line to GROUND based on a signal level on the first conductor;
a bit line disposed adjacent the first conductor; and
a control circuit coupled to the switching circuit, the control circuit configured to:
detect a leakage current in the switching circuit;
couple the bit line to an erase voltage;
couple the signal line to internally generated voltage source;
detect a drop in a voltage of the internally generated voltage source; and
determine that a coupling fault exists in the first conductor.