MODELLING AND PREDICTION OF VIRTUAL QUALITY CONTROL DATA INCORPORATING AREA LOCATION IN THE PRODUCTION OF MEMORY DEVICES

1 . A method, comprising:

receiving inline quality control data of test samples from manufacture of a plurality of examples of a wafer comprising multiple ones of an integrated circuit, the inline quality control data including area information on which of a plurality of distinct areas of the wafer that individual ones of the integrated circuits are formed;

receiving post-manufacturing test data of the test samples, the post-manufacturing test data of the test samples including the area information for the test samples;

creating a first virtual inline quality control data model for the manufacture of the wafer from the inline quality control data and the post-manufacturing test data, including the area information for the test samples for the inline quality control data and the post-manufacturing test data;

interpolating virtual inline quality control data including the area information for the manufacture of the wafer from the first virtual inline quality control data model and the post-manufacturing test data;

receiving an inline data report for the manufacture of the wafer;

creating a second virtual inline quality control data model including the area information for the manufacture of the wafer from the interpolated virtual inline quality control data and the inline data report; and

interpolating virtual inline quality control data including the area information for the manufacture of the wafer from the second virtual inline quality control data model and the inline data report.

2 . The method of claim 1 , wherein the post-manufacturing test data is from tests performed as part of a die sort test process.

3 . The method of claim 1 , wherein the inline quality control data includes critical dimension data values.

4 . The method of claim 1 , wherein the plurality of distinct areas of the wafer are a plurality commonly co-centered regions.

5 . The method of claim 1 , wherein the wafer comprises a bonded pair of separately formed wafers.

6 . The method of claim 5 , wherein a first of the separately formed wafers comprises a plurality of memory dies and a second of the separately formed wafers comprises a plurality of CMOS dies.

7 . The method of claim 1 , wherein receiving the inline quality control data of test samples includes performing tests on the test samples of the wafer.

8 . The method of claim 7 , wherein receiving the inline quality control data of test samples includes fabricating the test samples of the wafer.

9 . The method of claim 8 , wherein the test samples of the wafer are fabricated using a first set of processing parameters and the method further comprises:

based on the interpolated virtual inline quality control data for the manufacture of the wafer from the second virtual inline quality control data model and the inline data report, adjusting the first set of processing parameters; and

fabricating the wafer using the adjusted first set of processing parameters.

10 . The method of claim 8 , wherein the wafer comprises a bonded pair of wafers and fabricating the test sample of the wafer comprises:

forming a first wafer;

separately forming a second wafer; and

bonding the first wafer and the second wafer to form the bonded pair.

11 . The method of claim 10 , wherein the first wafer comprises a plurality of memory dies and the second wafer comprises a plurality of CMOS dies.

12 . The method of claim 10 , wherein forming the first wafer comprises forming circuitry on a first surface of the first wafer and fabricating the test sample of the wafer further comprises:

subsequent to forming a first wafer and prior to bonding the first wafer and second wafer to form the bonded pair, rotating the first wafer such that the first surface of the first wafer faces the second wafer.

13 . The method of claim 12 , wherein;

performing the tests on the test samples to obtain the inline quality control data of the wafer is performed on the first wafer prior to rotating the first wafer; and

the post-manufacturing test data of the test samples is obtained subsequent to bonding the first wafer and the second wafer.

14 . The method of claim 13 , wherein the post-manufacturing test data of the test samples is obtained using a coordinate axis for the first wafer that is reversed relative a coordinate axis for the first wafer used for performing the tests on the test samples to obtain the inline quality control data of the wafer.

15 . A method, comprising:

fabricating a plurality of a wafer comprising multiple ones of an integrated circuit using a first set of processing parameters;

creating a first virtual inline quality control data model for the fabrication of the wafer from inline quality control data of test samples of the wafer and post-fabrication test data of the test samples, both of the inline quality control data and post-fabrication test data including area information on which of a plurality of distinct areas of the wafer that individual ones of the integrated circuits are formed;

interpolating virtual inline quality control data for the fabrication of the wafer using the first set of processing parameters from the first virtual inline quality control data model and the post-fabrication test data;

creating a second virtual inline quality control data model for the fabrication of the wafer using the first set of processing parameters from the interpolated virtual inline quality control data and an inline data report for the fabrication of the wafer using the first set of processing parameters;

interpolating virtual inline quality control data for the fabrication of the wafer using the first set of processing parameters from the second virtual inline quality control data model and the inline data report;

based on the interpolated virtual inline quality control data for the fabrication of the wafer using the first set of processing parameters from the second virtual inline quality control data model and the inline data report, adjusting the first set of processing parameters; and

fabricating the wafer using the adjusted first set of processing parameters.

16 . The method of claim 15 , wherein the post-fabrication test data is from tests performed as part of a die sort test process.

17 . The method of claim 15 , wherein the inline quality control data includes critical dimension data values.

18 . The method of claim 15 , wherein the plurality of distinct areas of the wafer are a plurality commonly co-centered regions.

19 . The method of claim 15 , wherein the wafer comprises a bonded pair of separately formed wafers.

20 . A system, comprising:

one or more processors, the one or more processors configured to:

receive, from a fabrication facility, inline quality control data of test samples from manufacture of a plurality of examples of a wafer comprising multiple ones of an integrated circuit, the inline quality control data including area information on which of a plurality of distinct areas of the wafer that individual ones of the integrated circuits are formed;

receive post-manufacturing test data of the test samples, the post-manufacturing test data of the test samples including the area information for the test samples;

create a first virtual inline quality control data model for the manufacture of the wafer from the inline quality control data and the post-manufacturing test data, including the area information for the test samples for the inline quality control data and the post-manufacturing test data;

interpolate virtual inline quality control data including the area information for the manufacture of the wafer from the first virtual inline quality control data model and the post-manufacturing test data;

receive, from the fabrication facility, an inline data report for the manufacture of the wafer;

create a second virtual inline quality control data model including the area information for the manufacture of the wafer from the interpolated virtual inline quality control data and the inline data report; and

provide the second virtual inline quality control data model to the fabrication facility.