IP Library › Assignment 005660/0221
Patent Assignment
Reel/Frame 005660/0221

Release by Secured Party, Recorded at Reel 5562, Frame 0082, on 12-28-90 (See Record for Details).

Recorded: 1991-04-04 Pages: 9
Assignor
Assignee
Covered Properties (56)
Cmos Structure and Method Utilizing Retarded Electric Field for Minimum Latch-Up
Patent: 4,203,126 →
Application: 05/631,729 →
Cmos Structure and Method Utilizing Retarded Electric Field for Minimum Latch-Up
Patent: 4,161,417 →
Application: 05/842,683 →
Carrier and Test Socket for Leadless Integrated Circuit
Patent: 4,329,642 →
Application: 06/018,869 →
High Voltage Field Effect Transistor
Patent: 4,454,523 →
Application: 06/248,814 →
Method of Fabricating Mesa Mosfet Using Overhang Mask and Resulting Structure
Patent: 4,419,811 →
Application: 06/371,599 →
Methods for Forming Lateral and Vertical Dmos Transistors
Patent: 4,682,405 →
Application: 06/757,582 →
Power Supply Having Dual Ramp Control Circuit
Patent: 4,674,020 →
Application: 06/808,575 →
Insulated Gate Transistor with Latching Inhibited
Patent: 4,779,123 →
Application: 06/808,904 →
Integrated Buried Zener Diode and Temperature Compensation Transistor
Patent: 4,766,469 →
Application: 06/816,593 →
Method for Manufacturing a Power Mos Transistor
Patent: 4,798,810 →
Application: 06/838,217 →
Method for Making Planar Vertical Channel Dmos Structures
Patent: 4,767,722 →
Application: 06/843,454 →
Fabrication of Double Diffused Metal Oxide Semiconductor Transistor
Patent: 4,716,126 →
Application: 06/871,006 →
Manufacture of Trimmable High Value Polycrystalline Silicon Resistor
Patent: 4,707,909 →
Application: 06/894,418 →
Implantation of Ions into an Insulating Layer to Increase Planar Pn Junction Breakdown Voltage
Patent: 4,827,324 →
Application: 06/927,882 →
Method for Obtaining Regions of Dielectrically Isolated Single Crystal Silicon
Patent: 4,824,795 →
Application: 07/010,924 →
Method and Apparatus for Increasing Breakdown of a Planar Junction
Patent: 4,799,100 →
Application: 07/014,961 →
Method of Fabricating a High Voltage Semiconductor Device
Patent: 4,786,614 →
Application: 07/019,085 →
Switch Interface Circuit for Power Mosfet Gate Drive Control
Patent: 4,853,563 →
Application: 07/036,777 →
Power Dmos Transistor with High Speed Body Diode
Patent: 4,811,065 →
Application: 07/061,352 →
Limiting Shoot-Through Current in a Power Mosfet Half-Bridge During Intrinsic Diode Recovery
Patent: 4,841,166 →
Application: 07/074,903 →
Method for Reducing Current Gain of Parasitic High Voltage Bipolar Transistors
Application: 07/083,560 →
Ion Implantation of Thin Film CRSI2 and Sic Resistors
Patent: 4,759,836 →
Application: 07/084,541 →
Method of Fabricating a High Value Semiconductor Resistor
Patent: 4,843,027 →
Application: 07/088,157 →
Method of Bonding Semiconductor Wafers
Patent: 4,774,196 →
Application: 07/089,184 →
Doped SIO2 Resistor and Method of Forming Same
Patent: 4,868,537 →
Application: 07/095,288 →
Dense Vertical J-Mos Transistor
Patent: 4,791,462 →
Application: 07/095,481 →
Dual-Gate High Density Fet
Patent: 4,835,586 →
Application: 07/099,452 →
Vertical Current Flow Field Effect Transistor
Patent: 5,164,325 →
Application: 07/107,725 →
Buried Gate Jfet
Patent: 4,845,051 →
Application: 07/115,076 →
Method for Providing Dielectrically Isolated Circuit
Patent: 4,851,366 →
Application: 07/120,343 →
Method for Increasing the Performance of Trenched Devices and the Resulting Structure
Patent: 4,893,160 →
Application: 07/120,395 →
High Voltage Level Shift Semiconductor Device
Patent: 4,890,146 →
Application: 07/133,710 →
A Power Mos Transistor with Equipotential Ring
Patent: 4,816,882 →
Application: 07/138,989 →
Grooved Dmos Process with Varying Gate Dielectric Thickness
Patent: 4,914,058 →
Application: 07/138,999 →
Method for Improved Alignment for Semiconductor Devices with Buried Layers
Patent: 4,936,930 →
Application: 07/141,877 →
Trench Power Mosfet Device
Patent: 4,967,245 →
Application: 07/167,617 →
High Voltage Drifted-Drain Mos Transistor
Patent: 4,794,436 →
Application: 07/195,436 →
Lightly Doped Drain Mosfet with Reduced On-Resistance
Patent: 5,237,193 →
Application: 07/210,959 →
Planar Vertical Channel Dmos Structure
Patent: 5,034,785 →
Application: 07/235,842 →
Vertical Dmos Power Transistor with an Integral Operating Condition Sensor
Patent: 4,896,196 →
Application: 07/243,166 →
Power Transistor with Integrated Gate Resistor
Patent: 4,920,388 →
Application: 07/246,937 →
Complementary, Isolated Dmos Ic Technology
Patent: 5,156,989 →
Application: 07/268,839 →
Self-Aligned Ldd Lateral Dmos Transistor with High-Voltage Interconnect Capability
Patent: 5,055,896 →
Application: 07/285,842 →
Trench Dmos Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry
Patent: 5,072,266 →
Application: 07/290,546 →
Vertical Dmos Transistor Fabrication Process
Patent: 4,983,535 →
Application: 07/292,668 →
High Value Semiconductor Resistor
Patent: 4,893,166 →
Application: 07/313,737 →
Rugged Lateral Dmos Transistor Structure
Patent: 4,929,991 →
Application: 07/334,806 →
Method for Obtaining Low Interconnect Resistance on a Grooved Surface and the Resulting Structure
Patent: 4,916,509 →
Application: 07/336,619 →
Hall Sensing of Bond Wire Current
Patent: 5,017,804 →
Application: 07/340,445 →
Integrated Circuit with High Power, Vertical Output Transistor Capability
Patent: 4,956,700 →
Application: 07/356,631 →
Method and Apparatus for Improving the on-Voltage Characteristics of a Semiconductor Device
Patent: 4,952,992 →
Application: 07/406,844 →
Method of Fabricating a Short-Channel Low Voltage Dmos Transistor
Patent: 4,931,408 →
Application: 07/420,971 →
Mos Transistor with a Charge Induced Drain Extension
Patent: 5,108,940 →
Application: 07/451,518 →
Junction Field-Effect Transistor with a Novel Gate
Patent: 4,958,204 →
Application: 07/453,367 →
Optimization of Bv and Rds-on by Graded Doping in Ldd and Other High Voltage Ic
Patent: 5,132,753 →
Application: 07/498,170 →
Closed Cell Transistor with Built-in Voltage Clamp
Patent: 5,136,349 →
Application: 07/597,118 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Feb 5, 1981
From: WILLIAMS, CLAIR E.
To: SILICONIX INCORPORATED
Reel/Frame 003827/0206 →
Assignment of Assignors Interest. Mar 30, 1981
From: HILL, LORIMER K.
To: SILICONIX INCORPORATED, SANTA CLARA,CA.
Reel/Frame 003892/0446 →
Assignment of Assignors Interest. Apr 26, 1982
From: RICE, EDWARD J.
To: ACRIAN, INC., A CORP. OF CA
Reel/Frame 003999/0569 →
Assignment of Assignors Interest. Jul 22, 1985
From: BLANCHARD, RICHARD A.; PLUMMER, JAMES D.
To: SILICONIX, INC 2201 LAURELWOOD ROAD, SANTA CLARA, CA. 95054 A CORP. OF CA.
Reel/Frame 004440/0501 →
Assignment of Assignors Interest. Dec 13, 1985
From: BENCUYA, IZAK; COGAN, ADRIAN I.
To: SILICONIX INCORPORATED, A CORP OF CALIFORNIA
Reel/Frame 004516/0834 →
Assignment of Assignors Interest. Dec 13, 1985
From: HILL, LORIMER K.
To: SILICONIX INCORPORATED, 2201 LAURELWOOD ROAD, SANTA CLARA, CA., 95054, A CORP OF CALIFORNIA
Reel/Frame 004496/0119 →
Assignment of Assignors Interest. Jan 6, 1986
From: HILL, LORIMER K.
To: SILICONIX INCORPORATED
Reel/Frame 004503/0384 →
Assignment of Assignors Interest. Mar 10, 1986
From: BLANCHARD, RICHARD A.; COGAN, ADRIAN
To: SILICONIX INCORPORATED
Reel/Frame 004527/0606 →
Assignment of Assignors Interest. Mar 24, 1986
From: BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED, A CORP. OF CA.
Reel/Frame 004531/0554 →
Assignment of Assignors Interest. Jun 5, 1986
From: COGAN, ADRIAN I.
To: SILICONIX INCORPORATED
Reel/Frame 004569/0247 →
Assignment of Assignors Interest. Aug 8, 1986
From: BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED, A CORP. OF CA.
Reel/Frame 004590/0064 →
Assignment of Assignors Interest. Oct 14, 1986
From: ACRIAN, INC.,
To: SILICONIX INCORPORATED
Reel/Frame 004613/0870 →
Assignment of Assignors Interest. Nov 6, 1986
From: BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED, A CORP OF CA.
Reel/Frame 004633/0583 →
Assignment of Assignors Interest. Feb 5, 1987
From: BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED, A CORP OF CA.
Reel/Frame 004666/0071 →
Assignment of Assignors Interest. Feb 17, 1987
From: BLANCHARD, RICHARD A.; COGAN, ADRIAN I.
To: SILICONIX INCORPORATED, A CA. CORP.
Reel/Frame 004671/0162 →
Assignment of Assignors Interest. Feb 26, 1987
From: COGAN, ADRIAN I.
To: SILICONIX INCORPORATED
Reel/Frame 004682/0969 →
Assignment of Assignors Interest. Apr 10, 1987
From: HILL, LORIMER K.; HARNDEN, JAMES A.; CONCKLIN, BARRY J.
To: SILICONIX INCORPORATED, A DE. CORP.
Reel/Frame 004709/0265 →
Assignment of Assignors Interest. Jun 11, 1987
From: COGAN, ADRIAN I.
To: SILICONIX INCORPORATED, A DE. CORP.
Reel/Frame 004727/0614 →
Merger Effective March 5, 1987, Delaware Jun 22, 1987
From: SILICONIX INCORPORATED, A CA CORP
To: SILICONIX INCORPORATED, A DE. CORP.
Reel/Frame 004727/0976 →
Assignment of Assignors Interest. Aug 7, 1987
From: WILLIAMS, RICHARD K.; BUSSE, ROBERT W.; BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED
Reel/Frame 004758/0280 →
Assignment of Assignors Interest. Aug 12, 1987
From: HILL, LORIMER K.; CHIN, BARRY L.; BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED
Reel/Frame 004769/0410 →
Assignment of Assignors Interest. Aug 21, 1987
From: GEEKIE, JAMES
To: SILICONIX INCORPORATED
Reel/Frame 004774/0560 →
Assignment of Assignors Interest. Aug 25, 1987
From: BLANCHARD, RICHARD A.
To: SILICONIX INCORPORATED, A CORP. OF DE
Reel/Frame 004781/0045 →
Assignment of Assignors Interest. Aug 28, 1987
From: HARNDEN, JAMES A.
To: SILICONIX INCORPORATED
Reel/Frame 004751/0157 →
Assignment of Assignors Interest. Sep 10, 1987
From: BLANCHARD, RICHARD A.; COGAN, ADRIAN I.
To: SILICONIX INCORPORATED, A DE CORP.
Reel/Frame 004765/0235 →