IP Library › Assignment 007194/0606
Patent Assignment
Reel/Frame 007194/0606

Change of Name

Recorded: 1994-11-07 Pages: 52
Assignor
Assignee
SAMSUNG ELECTRONICS CO., LTD.
416 MAETAN-DONG PALTAL-GU, SUWON CITY KOREA, SUWON CITY, KOREA, REPUBLIC OF
Covered Properties (39)
A Lsi Programmable Processor
Patent: 3,878,514 →
Application: 05/307,863 →
Overlap Timing Control Circuit for Conditioning Signals in a Semicondu Ctor Memory
Patent: 3,866,061 →
Application: 05/391,963 →
Multi-Microprocessor Unit on a Single Semiconductor Chip
Patent: 3,980,992 →
Application: 05/527,358 →
Fifo Buffer Register Memory Utilizing a Oneshot Data Transfer System
Patent: 3,953,838 →
Application: 05/537,680 →
Capacittor Memory Cell
Patent: 4,021,788 →
Application: 05/578,094 →
Ultra High Sensitivity Sense Amplifier for Memories Employing Single T Ransistor Cells
Patent: 4,031,522 →
Application: 05/594,579 →
Interlaced Memory Matrix Array Having Single Transistor Cells
Patent: 4,025,907 →
Application: 05/594,669 →
Mos Integrated Circuit Chip for Display
Patent: 3,997,813 →
Application: 05/630,218 →
Method for Making Transistor Structures
Patent: 4,038,107 →
Application: 05/637,177 →
High Speed Differential to Ttl Converter
Patent: 4,045,690 →
Application: 05/658,705 →
Dynamic Memory Refresh Method
Patent: 4,040,122 →
Application: 05/674,391 →
Igfet Integrated Circuit Memory Cell
Patent: 4,125,933 →
Application: 05/792,578 →
Organization for an Integrated Circuit Calculator/Controller
Patent: 4,155,118 →
Application: 05/834,928 →
Method of Making a V-Mosfield Effect Transistor for Dynamic Memory Ce Ll Having Improved Capacitance
Patent: 4,116,720 →
Application: 05/864,247 →
Compensated Mos Timing Network
Patent: 4,199,693 →
Application: 05/875,783 →
Igfet Integrated Circuit Memory Cell
Patent: 4,141,027 →
Application: 05/907,725 →
High Speed, Low Component Count, Cml Exclusive nor Gate
Patent: 4,281,258 →
Application: 05/958,255 →
Method of Forming a Metal Interconnect Structure for Integrated Circuits
Patent: 4,158,613 →
Application: 05/966,326 →
Oxidation of Silicon Wafers to Eliminate White Ribbon
Patent: 4,401,691 →
Application: 05/970,580 →
Decoder for a Prom
Patent: 4,195,358 →
Application: 05/973,175 →
Technique of Growing Thin Silicon Oxide Films
Patent: 4,214,919 →
Application: 05/973,928 →
Single Mask Method of Fabricating Complementary Integrated Circuits
Patent: 4,244,752 →
Application: 06/017,842 →
Charge Restore Circuit for Semiconductor Memories
Patent: 4,262,342 →
Application: 06/053,084 →
Ram Having a Stabilized Substrate Bias and Low-Threshold Narrow-Width Transfer Gates
Patent: 4,262,298 →
Application: 06/072,446 →
Fabrication of Integrated Circuits Employing Only Ion Implantation for All Dopant Layers
Patent: 4,261,763 →
Application: 06/080,618 →
Method for Mass Producing Miniature Field Effect Transistors in High Density Lsi/Vlsi Chips
Patent: 4,354,307 →
Application: 06/099,515 →
Method of Fabricating a Charge Transfer Channel Covered by a Stepped Insulating Layer
Patent: 4,313,253 →
Application: 06/113,388 →
Hermetic Integrated Circuit Package for High Density High Power Applications
Patent: 4,338,621 →
Application: 06/118,496 →
Method of Fabricating a Misaligned, Composite Electrical Contact on a Semiconductor Substrate
Patent: 4,381,215 →
Application: 06/153,090 →
Electronic Package for High Density Integrated Circuits
Patent: 4,296,456 →
Application: 06/155,533 →
Jfet Dynamic Memory
Patent: 4,423,490 →
Application: 06/200,997 →
Field Effect Current Mode Logic Gate
Patent: 4,445,051 →
Application: 06/277,629 →
Extended Address Generating Apparatus and Method
Patent: 4,453,212 →
Application: 06/282,919 →
Semiconductor Die-Attach Technique and Composition Therefor
Patent: 4,487,638 →
Application: 06/444,267 →
Re-Programmable Pla
Patent: 4,508,977 →
Application: 06/457,175 →
Content Addressable Memory Cell
Patent: 4,532,606 →
Application: 06/513,393 →
High Capacity Memory Cell Having a Charge Transfer Channel Covered by a Stepped Insulating Layer
Patent: 4,482,908 →
Application: 06/576,763 →
Alluminum - Refractory Metal Interconnect W/Anodized Periphery
Patent: 4,531,144 →
Application: 06/580,291 →
Epoxy-Glass Integrated Circuit Package Having Bonding Pads in a Stepped Cavity
Patent: 4,643,935 →
Application: 06/819,995 →
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger Delaware Effective May 30, 1982. Jul 13, 1984
From: BURROUGHS CORPORATION A CORP OF MI (MERGED INTO); BURROUGHS DELAWARE INCORPORATED A DE CORP. (CHANGED TO)
To: BURROUGHS CORPORATION
Reel/Frame 004312/0324 →
Security Interest Jul 5, 1985
From: DUCON COMPANY, INC., THE, A NY CORP
To: MARINE MIDLAND BANK N.A.
Reel/Frame 004434/0890 →
Assignment of Assignors Interest. Sep 26, 1988
From: UNISYS CORPORATION, A CORP. OF DE.
To: SAMSUNG SEMICONDUCTOR AND TELECOMMUNICATIONS, LTD. ("SST")
Reel/Frame 004998/0745 →
Assignment of Assignors Interest. Nov 1, 1988
From: BURROUGHS CORPORATION
To: SAMSUNG SEMICONDUCTOR AND TELECOMMUNICATIONS, LTD. 259, KONGDAN-DONG, GUMI-SI, KYUNG-SANGBUK-DO, KOREA, A REP. OF KOREA CORP.
Reel/Frame 004990/0682 →